FB_B1

PG_B1

PG_B4

FB_B4

AVDD

BYP

AGND

PG_B2

EN_B2

FB_B2

DEFSEL

FB_B3

EN_B3

PG_B3

CIN2

L2

COUT2

CIN1

COUT1

L1

COUT3

CIN3

COUT4

CIN4

L4

L3

Route to

controller

Connect thermal pad

to GND plane using

multiple vias

VOUT1

VOUT2

VOUT3

VOUT4

CBYP

CIN

Route to

Controller on

internal layers

Route to

Controller on

internal layers

Vias to

VIN plane

Vias to

VIN plane

Vias to

VIN plane

Vias to

VIN plane

Vias to

GND plane

Vias to

GND plane

LP8728B-Q1

SNVSA70 – FEBRUARY 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

•

AVDD and BYP pins must be bypassed to ground. 1-µF ceramic capacitor is recommended. Place the

capacitors close to the AVDD, BYP, and AGND pins.

•

AGND pin must be tied to the PCB ground plane. Use multiple vias to minimize the inductance.

•

AVDD pin must be connected to PCB VIN plane. Use multiple vias to minimize the inductance.

•

Place the buck converter input capacitors as close to the buck input voltage and buck ground pins as

possible.

•

Place the buck converter output capacitors and inductors so that the buck converter switching loops can be

routed on top layer. Try to minimize the area of the switching loops.

•

Keep the trace width from switch pin to inductor wide enough to withstand the switching currents. Avoid any

excess copper on the switch node to minimize parasitic switch node capacitance.

•

Connect the exposed thermal pad to ground plane with multiple thermal vias.

•

Avoid routing digital signals directly under the switching loops to avoid interferences.

10.2 Layout Example

Figure 21. LP8728B-Q1 Layout Example

18

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