Normal Operation

EN_Bx = HIGH

& VIN > UVLO

Shutdown

Mode

Reference

Startup

(420 µs typ)

EN_Bx = HIGH

Active Mode

Buck_X

Startup

Buck_X

Shutdown

All EN_Bx pins

are LOW

EN_Bx = LOW

Reference

Shutdown

All EN_Bx pins

not LOW

VOUTX falls below

power good threshold

PG_Bx is pulled

low

Power-up

Sequence

Fault

UVLO, OVP or

TSD Fault

Fault < 5 ms

Fault > 5 ms

LP8728B-Q1

SNVSA70 – FEBRUARY 2015

www.ti.com

Device Functional Modes (continued)

If OVP, or TSD fault occurs during normal operation, all power good pins are pulled low. Once fault condition has

lasted for 5 ms all buck converters are shut down. In case of UVLO fault buck regulators are instantly shut down.

Once fault condition has ended buck converters are restarted in a Buck1

→ Buck2 → Buck3 → Buck4 power-up

sequence. A 500-µs delay is included between each buck start-up. In case of TSD fault there is a 2-second

safety delay before power-up sequence.

Figure 14. Device Functional Modes

14

Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: LP8728B-Q1