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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP5562 датащи(PDF) 6 Page - Texas Instruments |
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LP5562 датащи(HTML) 6 Page - Texas Instruments |
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6 / 52 page  6 LP5562 SNVS820B – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: LP5562 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated (1) The I2C host should allow at least 1ms before sending data to the LP5562 after the rising edge of the enable line. 6.6 Logic Interface Characteristics Unless otherwise specified: limits for typical values are for TA = 25°C and minimum and maximum limits apply over the operating ambient temperature range ( −40°C < TA < +85°C); VEN = 1.65 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT EN VIL Input low level 0.5 V VIH Input high level 1.2 V II Logic input current –1 1 µA tDELAY Input delay(1) 2 µs LOGIC INPUT SCL, SDA, CLK_32K, ADDR_SEL0, ADDR_SEL1, VEN = 1.8 V VIL Input low level 0.2 × VEN V VIH Input high level 0.8 × VEN V II Input current –1 1 µA ƒCLK_32K Clock frequency 32 kHz ƒSCL Clock frequency 400 kHz LOGIC OUTPUT SDA VOL Output low level IOUT = 3 mA (pullup current) 0.3 0.5 V IL Output leakage current 1 µA (1) Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD. (2) The ideal external clock signal for the LP5562 is a 0 V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz, program execution will be faster and at frequencies below 32.7 kHz program execution will be slower. 6.7 Recommended External Clock Source Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT CLK_32K ƒCLK_32K Clock frequency 32.7 kHz tCLKH High time 6 µs tCLKL Low time 6 µs tr Clock rise time 10% to 90% 2 µs tf Clock fall time 90% to 10% 2 µs (1) Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD. 6.8 I 2C Timing Requirements (SDA, SCL) See (1) MIN MAX UNIT ƒSCL Clock frequency 400 kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Setup time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 20 + 0.1Cb 300 ns 8 Fall time of SDA and SCL 15 + 0.1Cb 300 ns 9 Set-up time for STOP condition 600 ns 10 Bus-free time between a STOP and a START condition 1.3 µs Cb Capacitive load for each bus line 10 200 pF |
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