LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

www.ti.com

SPI register access allows the SDO0 and SDO1 outputs to be manually selected instead of using the BYPASS,

MUTE, and SCO_EN functions. Upon entering SPI mode, the SDO0 and SDO1 outputs will be configured by

register 0x12 bits 2:0 (BYPASS, MUTE, and SCO_EN). Register 0x09 bit 5 (PIN_MODE_OV) can be used to

override this control and choose manual SDO0 and SDO1 output selection. Once this override bit is set, then

register 0x1E bits 6:5 (SDO0_SEL) select the output for SDO0 according to Table 3, and register 0x1E bits 4:3

(SDO1_SEL) select the output for SDO1 according to Table 4. Note that register 0x09 bit 5 (PIN_MODE_OV)

overrides the use of register 0x12 bits 1:0 (MUTE and SCO_EN), but register 0x12 bit 2 (BYPASS), will still

operate and can be used to bypass reclocking for both outputs.

Table 3. SDO0 Manual Output Selection (via Register 0x1E bits 6:5)

SDO0_SEL[1:0]

SDO0 Output

Lock Detect = 1

Lock Detect = 0

00

Reclocked data

Bypassed data

01

Bypassed data

Bypassed data

10

Muted

Muted

11

Reclocked data

Bypassed data

Table 4. SDO1 Manual Output Selection (via Register 0x1E bits 4:3)

SDO1_SEL[1:0]

SDO1 Output

Lock Detect = 1

Lock Detect = 0

00

Recovered clock

Muted

01

Reclocked data

Bypassed data

10

Muted

Muted

11

Bypassed data

Bypassed data

Data Rate Selection

The LMH0366 can be configured for automatic or manual rate selection, which is controlled either by the RATE0

and RATE1 pins or through SPI register access. With default register settings, the RATE0 and RATE1 pins

select the allowable rates at which the reclocker will lock, as shown in Table 5. The RATE0 and RATE1 pins

have internal pulldowns to select auto-rate detect by default.

Table 5. Data Rate Selection

RATE1

RATE0

Selected Rate or Mode

0

0

Auto-rate detect – video rates (270, 1483.5, 1485, 2967, 2970 Mbps)

0

1

270 Mbps

1

0

1483.5/1485 Mbps, 2967/2970 Mbps

1

1

125 Mbps

Upon entering SPI mode, the RATE pins will continue to select the allowable rates at which the reclocker will

lock. Setting register 0x1D bit 0 (RATE_SEL_OV) overrides this selection and allows the rate selection to be

controlled by register 0x1C bits 1:0 (RATE_SEL) instead of the RATE pins. (This frees up the RATE0 and

RATE1 pins to be used as GPIOs since they are no longer needed for rate selection.)

External Clock Reference or Referenceless Mode

The LMH0366 can operate with an external 27 MHz crystal or external clock signal as a timing reference input

(external reference mode), or it can operate with no reference at all (referenceless mode). Providing an external

27 MHz reference allows the LMH0366 to distinguish between 2.97 Gbps and 2.97/1.001 Gbps, and between

1.485 Gbps and 1.485/1.001 Gbps. This reference could be a 27 MHz parallel resonant crystal and load network

connected to the XTAL_IN and XTAL_OUT pins, or a 27 MHz 2.5V LVCMOS compatible clock signal connected

to XTAL_IN. The LMH0366 will automatically detect the 27 MHz reference clock and indicate its presence via

register 0x41 bit 3 (REF_CLK_DET).

When using the LMH0366 in referenceless mode (i.e. no external 27 MHz crystal or reference clock applied), the

XTAL_IN pin must be connected to ground (VEE).

12

Submit Documentation Feedback

Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: LMH0366