1

4

3

2

LMH0366

(top view)

18

15

16

17

10

7

8

9

21

24

23

22

5

6

12

11

13

14

19

20

DAP = VEE

SDI

SDI

MOSI

SCK

GPIO1

ENABLE

SDO1

SDO1

SDO0

SDO0

VCC

SD/HD

LMH0366

www.ti.com

SNAS585D – APRIL 2012 – REVISED APRIL 2013

The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the

negative power supply voltage.

Figure 2. SPI Mode / SPI_EN = VCC

24-Pin

See Package Number RTW0024A

PIN DESCRIPTIONS – PIN MODE (NON-SPI) / SPI_EN = GND

Pin

Name

I/O, Type

Description

1, 24

RATE1, RATE0

I, LVCMOS

Data rate select inputs. RATE0 and RATE1 each has an internal pulldown.

2, 3

SDI, SDI

I, SDI

Serial data differential input.

4

ENABLE

I, LVCMOS

Device enable. This pin has an internal pullup.

H = Device enabled (normal operation).

L = Device powered down.

5

BYPASS

I, LVCMOS

Reclocker bypass. This pin has an internal pulldown.

H = Reclocking bypassed.

L = Normal operation.

6

MUTE

I, LVCMOS

Output mute. This pin has an internal pullup.

H = Normal operation.

L = SDO0 and SDO1 outputs are muted.

7

SPI_EN

I, LVCMOS

SPI register access enable. This pin has an internal pulldown.

H = SPI register access mode.

L = Pin mode.

8

XTAL_IN

I, ANALOG

External crystal or clock input for optional 27 MHz external reference. When not used

(i.e. referenceless mode), connect to ground.

10

XTAL_OUT

O, ANALOG

External crystal or clock output.

11

LOCK_DETECT O, LVCMOS

PLL lock detect status.

H = PLL locked.

L = PLL not locked.

13, 14

SDO1, SDO1

O, LVDS

Serial data differential output 1.

16, 17

SDO0, SDO0

O, LVDS

Serial data differential output 0.

18

SD/HD

O, LVCMOS

Data rate range indication.

H = Locked data rate is SD.

L = Locked data rate is 3G or HD (or PLL unlocked).

Copyright © 2012–2013, Texas Instruments Incorporated

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