LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

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The signal that goes to the eye opening monitor and also to the bypassed data for the SDO1 output can either

be equalized or it can bypass the FR4 equalizer (see Block Diagram). By default, this signal is equalized, but

register 0x14 bit 1 (MUX2_EQ_SEL) selects between non-equalized or equalized data (before or after the FR4

equalizer) for this signal.

Input Signal Detection

The input includes a signal detect circuit accessible via the SPI. The status of the input signal detection is

indicated either by register 0x01 bit 0 (SIG_DET) or register 0x03 bit 4 (SIG_DET).

The signal detection threshold is adjustable via register 0x20 bits 5:3 (SIG_DET_LVL).

The signal detection status can optionally be indicated via the GPIO pins (see the General Purpose Input/Output

Pins (GPIO[3:0]) section).

Serial Data Output

The LMH0366 provides two internally terminated 100

Ω LVDS outputs: SDO0 and SDO1.

The SDO0 output provides either serial reclocked data or bypassed data. The SDO1 output provides either serial

reclocked data, the recovered serial clock, or bypassed data.

The LMH0366 output should be DC coupled to the input of the receiving device where possible. 100

Ω

transmission lines should be used to connect between the LMH0366 outputs and the input of the receiving

device. The LMH0366 output should not be DC coupled to CML inputs. If there are strong pullup resistors (e.g.

50

Ω) at the receiving device, AC coupling should be used.

The output driver swing (amplitude), offset voltage (common mode voltage), and de-emphasis level are

adjustable via the SPI. In addition, SPI register access allows the signal polarity of the output drivers to be

inverted and the output drivers to be independently powered down.

Output Swing (VOD)

The default peak-to-peak differential output voltage is 800 mVP-P. The output swing is individually adjustable for

the two output drivers via register 0x12 bits 7:6 (SDO0_VOD) and bits 5:4 (SDO1_VOD). The output swing may

be selected between 400 mVP-P, 530 mVP-P, 670 mVP-P, and 800 mVP-P.

Offset Voltage (VOS)

The default offset voltage is 1.2V. The offset voltage is adjustable via register 0x11 bits 7:6 (SDO_VOS). The

offset voltage may be selected between 0.8V, 1.0V, and 1.2V. This setting applies to both the SDO0 and SDO1

output drivers.

Output De-Emphasis

Output de-emphasis compensates for board trace losses. The output driver de-emphasis is turned off (0 dB) by

default. The output de-emphasis is individually adjustable for the two output drivers via register 0x13 bits 7:6

(SDO0_DEM) and bits 5:4 (SDO1_DEM). The output de-emphasis may be selected between 0 dB (no-de-

emphasis, for driving up to 10” FR4), 3 dB (for driving 10-20” FR4), 5 dB (for driving 20-30” FR4), and 7 dB (for

driving 30-40” FR4).

Output Polarity Inversion

The output polarity of both output drivers can be inverted via register 0x11 bit 0 (SDO_INV). This may be useful

to preserve the proper signal polarity for polarity sensitive applications (e.g. DVB-ASI) in which the polarity of the

reclocker’s input or output signal needs to be swapped for layout reasons.

Output Power Down

The output drivers may be individually powered down via register 0x11 bit 4 (SDO0_PD) and bit 3 (SDO1_PD).

Lock Detect

The lock detect indicates when the reclocker is locked to the incoming data stream. The lock detection status can

be monitored by the active-high LOCK_DETECT pin, or by reading register 0x01 bit 4 (LOCK_DET). Note that

when the bypass mode is active, lock detect will not assert. See Table 2.

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