LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

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Power Supply Recommendations

The LMH0366 requires a single 2.5V power supply. Circuit board layout and stack-up for the LMH0366 should be

optimized to minimize noise to the device from switching power supplies or nearby high speed devices.

It is recommended to provide power to the LMH0366 using a linear regulator. If a switching regulator used, the

power supply filtering must be adequate to filter the switching noise.

The following guidelines are recommended for supplying power to the LMH0366:

•

Bypass/decouple each supply pin with a high frequency ceramic bypass capacitor (0.01 µF to 0.1 µF) placed

as close as possible to the pin.

•

Deploy nearby bulk capacitors (2.2 µF to 22 µF) for additional power supply filtering.

•

Wherever possible, use two vias for each connection to internal power and ground planes to minimize the via

parasitics.

•

Use the capacitance of the power-ground system for extra bypassing by using thin dielectrics between the

power and ground planes.

•

Route high speed differential lines away from the device power pins to avoid coupling noise into the power

supply lines.

Loop Filter Recommendations

The LMH0366 uses a 56 nF capacitor for the loop filter, connected between the LF1 and LF2 pins. Alternately, a

47 nF capacitor may be used in place of this 56 nF capacitor.

The loop filter layout should be optimized to minimize coupling between the loop filters of different devices and

also to avoid noise pick up from other signals. The external loop filter capacitor should be connected as close to

the device pins as possible and with maximum isolation from other signals.

It is important to keep multiple reclockers as isolated from one another as possible to avoid any interaction

between the loop filters or other sensitive circuits.

The following guidelines are recommended for the loop filter layout:

•

Keep the loop filter traces as short as possible; place the loop filter capacitor parallel to the device to allow for

the shortest trace interconnect.

•

Avoid using vias between the loop filter pins and the external loop filter capacitor.

•

Remove the ground plane underneath the LF1 and LF2 pins and also in the area underneath the loop filter

capacitor to increase isolation.

•

Avoid running traces under the loop filter area as much as possible to increase isolation.

•

When using multiple devices, place the devices as far apart from one another as possible. Avoid placing the

loop filter pins of different devices next to each other.

Interfacing to 3.3V SPI

The LMH0366 may be controlled via optional SPI register access. The LMH0366 SPI pins support 2.5V

LVCMOS logic levels and are compliant with JEDEC JESD8-5. Care must be taken when interfacing the SPI pins

to other voltage levels.

The 2.5V LMH0366 SPI pins may be interfaced to a 3.3V compliant SPI host by using a voltage divider or level

translator. One implementation is a simple resistive voltage divider as shown in Figure 12.

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