LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

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PIN DESCRIPTIONS – PIN MODE (NON-SPI) / SPI_EN = GND (continued)

Pin

Name

I/O, Type

Description

19

SCO_EN

I, LVCMOS

Serial clock output enable for SDO1. This pin has an internal pulldown.

H = SDO1 output is serial clock.

L = SDO1 output is serial data.

22, 23

LF1, LF2

I, Analog

Loop filter. Connect a 56 nF capacitor between LF1 and LF2.

15

VCC

Power

Positive power supply (2.5V).

DAP, 9, 12,

VEE

Ground

Negative power supply (ground).

20, 21

PIN DESCRIPTIONS – SPI MODE / SPI_EN = VCC

Pin

Name

I/O, Type

Description

1, 24

GPIO1, GPIO0

I/O, LVCMOS

General purpose input/output pins, selectable via the SPI. Pins 24 and 1 will operate as

RATE0 and RATE1 inputs (the same as while in pin mode), with internal pulldowns,

unless configured differently via the SPI.

2, 3

SDI, SDI

I, SDI

Serial data differential input.

4

ENABLE

I, LVCMOS

Device enable. This pin has an internal pullup.

H = Device enabled (normal operation).

L = Device powered down.

5

MOSI (SPI)

I, LVCMOS

SPI master output / slave input. LMH0366 data receive. This pin has an internal pullup.

6

SCK (SPI)

I, LVCMOS

SPI serial clock input.

7

SPI_EN

I, LVCMOS

SPI register access enable. This pin has an internal pulldown.

H = SPI register access mode.

L = Pin mode.

8

XTAL_IN

I, ANALOG

External crystal or clock input for optional 27 MHz external reference. When not used

(i.e. referenceless mode), connect to ground.

10

XTAL_OUT

O, ANALOG

External crystal or clock output.

11

LOCK_DETECT O, LVCMOS

PLL lock detect status.

H = PLL locked.

L = PLL not locked.

13, 14

SDO1, SDO1

O, LVDS

Serial data differential output 1.

16, 17

SDO0, SDO0

O, LVDS

Serial data differential output 0.

18

SD/HD

O, LVCMOS

Data rate range indication.

H = Locked data rate is SD.

L = Locked data rate is 3G or HD (or PLL unlocked).

19

SS (SPI)

I, LVCMOS

SPI slave select. This pin has an internal pullup.

20

MISO (SPI)

O, LVCMOS

SPI master input / slave output. LMH0366 data transmit.

22, 23

LF1, LF2

I, Analog

Loop filter. Connect a 56 nF capacitor between LF1 and LF2.

15

VCC

Power

Positive power supply (2.5V).

DAP, 9, 12, 21 VEE

Ground

Negative power supply (ground).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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