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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86FS28DFG датащи(PDF) 189 Page - Toshiba Semiconductor |
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TMP86FS28DFG датащи(HTML) 189 Page - Toshiba Semiconductor |
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189 / 272 page  Page 177 TMP86FS28DFG 13.9 Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART0SR<PERR> is set to “1”. The UART0SR<PERR> is cleared to “0” when the RD0BUF is read after reading the UART0SR. Figure 13-5 Generation of Parity Error 13.9.2 Framing Error When “0” is sampled as the stop bit in the receive data, framing error flag UART0SR<FERR> is set to “1”. The UART0SR<FERR> is cleared to “0” when the RD0BUF is read after reading the UART0SR. Figure 13-6 Generation of Framing Error 13.9.3 Overrun Error When all bits in the next data are received while unread data are still in RD0BUF, overrun error flag UART0SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD0BUF are not affected. The UART0SR<OERR> is cleared to “0” when the RD0BUF is read after reading the UART0SR. Parity Stop Shift register pxxxx0* 1pxxxx0 xxxx0** RXD0 pin UART0SR<PERR> INTRXD0 interrupt After reading UART0SR then RD0BUF clears PERR. Final bit Stop Shift register xxxx0* 0xxxx0 xxx0** RXD0 pin UART0SR<FERR> INTRXD0 interrupt After reading UART0SR then RD0BUF clears FERR. |
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