DSP56321 datasheet(71/84 Pages) FREESCALE

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DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

A-7

M_CD EQU $FFF

; Clock Divider Mask (CD0-CD11)

M_COD EQU 12

; Clock Out Divider

M_SCP EQU 13

; Clock Prescaler

M_RCM EQU 14

; Receive Clock Mode Source Bit

M_TCM EQU 15

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;

;------------------------------------------------------------------------

;

M_TX00 EQU $FFFFBC

; SSI0 Transmit Data Register 0

M_TX01 EQU $FFFFBB

; SSIO Transmit Data Register 1

M_TX02 EQU $FFFFBA

; SSIO Transmit Data Register 2

M_TSR0 EQU $FFFFB9

; SSI0 Time Slot Register

M_RX0 EQU $FFFFB8

; SSI0 Receive Data Register

M_SSISR0 EQU $FFFFB7

; SSI0 Status Register

M_CRB0 EQU $FFFFB6

; SSI0 Control Register B

M_CRA0 EQU $FFFFB5

; SSI0 Control Register A

M_TSMA0 EQU $FFFFB4

; SSI0 Transmit Slot Mask Register A

M_TSMB0 EQU $FFFFB3

; SSI0 Transmit Slot Mask Register B

M_RSMA0 EQU $FFFFB2

; SSI0 Receive Slot Mask Register A

M_RSMB0 EQU $FFFFB1

; SSI0 Receive Slot Mask Register B

;

M_TX10 EQU $FFFFAC

; SSI1 Transmit Data Register 0

M_TX11 EQU $FFFFAB

; SSI1 Transmit Data Register 1

M_TX12 EQU $FFFFAA

; SSI1 Transmit Data Register 2

M_TSR1 EQU $FFFFA9

; SSI1 Time Slot Register

M_RX1 EQU $FFFFA8

; SSI1 Receive Data Register

M_SSISR1 EQU $FFFFA7

; SSI1 Status Register

M_CRB1 EQU $FFFFA6

; SSI1 Control Register B

M_CRA1 EQU $FFFFA5

; SSI1 Control Register A

M_TSMA1 EQU $FFFFA4

; SSI1 Transmit Slot Mask Register A

M_TSMB1 EQU $FFFFA3

; SSI1 Transmit Slot Mask Register B

M_RSMA1 EQU $FFFFA2

; SSI1 Receive Slot Mask Register A

M_RSMB1 EQU $FFFFA1

; SSI1 Receive Slot Mask Register B

;

SSI Control Register A Bit Flags

M_PM EQU $FF

; Prescale Modulus Select Mask (PM0-PM7)

M_PSR EQU 11

; Prescaler Range

M_DC EQU $1F000

; Frame Rate Divider Control Mask (DC0-DC7)

M_ALC EQU 18

; Alignment Control (ALC)

M_WL EQU $380000

; Word Length Control Mask (WL0-WL7)

M_SSC1 EQU 22

; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

; Serial Output Flag Mask

M_OF0 EQU 0

; Serial Output Flag 0

M_OF1 EQU 1

; Serial Output Flag 1

M_SCD EQU $1C

; Serial Control Direction Mask

M_SCD0 EQU 2

; Serial Control 0 Direction

M_SCD1 EQU 3

; Serial Control 1 Direction

M_SCD2 EQU 4

; Serial Control 2 Direction

M_SCKD EQU 5

; Clock Source Direction

M_SHFD EQU 6

; Shift Direction

M_FSL EQU $180

; Frame Sync Length Mask (FSL0-FSL1)

M_FSL0 EQU 7

; Frame Sync Length 0

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