DSP56321 datasheet(62/84 Pages) FREESCALE

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DSP56321 Technical Data, Rev. 11

4-2

Freescale Semiconductor

Design Considerations

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is

measured from the junction to the point at which the leads attach to the case.

•

If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is

computed from the value obtained by the equation (TJ – TT)/PD.

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first

definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case

thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case

thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will

yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric,

thermal characterization parameter or

ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of

the junction temperature in natural convection when the surface temperature of the package is used. Remember that

surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the

sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-

gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

Use the following list of recommendations to ensure correct DSP operation.

•

Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the

board ground to each GND pin.

•

Use at least four 0.01–0.1

µF bypass capacitors for V

CCQL (core) and at least six 0.01–0.1

µF bypass

capacitors for the other VCC (I/O) power connections positioned as closely as possible to the four sides of

the package to connect the power sources to GND.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins

are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for VCC and GND.

•

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This

recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD,

, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages

this

high-impedance

circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or VCC).

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