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DSP56321 датащи(PDF) 32 Page - Freescale Semiconductor, Inc

номер детали DSP56321
подробное описание детали  24-Bit Digital Signal Processor
PDF  84 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56321 датащи(HTML) 32 Page - Freescale Semiconductor, Inc

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DSP56321 Technical Data, Rev. 11
2-12
Freescale Semiconductor
Specifications
115 Address valid to RD
assertion
—0.5
× TC −2.0
0.5
0.3
0.1
–0.18
ns
116 RD assertion pulse width
(WS + 0.25)
× TC −3.0
[WS
≥ 3]
13.25
11.59
10.55
8.81
ns
117 RD deassertion to
address not valid
—1.25
× TC −4.0
[3
≤WS ≤7]
2.25
× T
C −4.0
[WS
≥ 8]
2.25
7.25
1.69
6.24
1.21
5.38
0.54
4.18
ns
ns
118 TA setup before RD or
WR deassertion5
—0.25
× T
C + 2.0
3.25
3.14
3.04
2.91
ns
119 TA hold after RD or WR
deassertion
0
—0
—0
0
ns
Notes:
1.
WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,
for a category of [3
≤WS ≤7] timing is specified for 3 wait states.) Three wait states is the minimum value otherwise.
2.
Timings 100 and 107 are guaranteed by design, not tested.
3.
All timings are measured from 0.5
× V
CCQH to 0.5 × VCCQH.
4.
The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a minimal
number of wait states.
5.
Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
Figure 2-10.
SRAM Read Access
Table 2-8.
SRAM Timing (Continued)
No.
Characteristics
Symbol
Expression1
200 MHz
220 MHz
240 MHz
275 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
A[0–17]
RD
WR
D[0–23]
AA[0–3]
105
106
113
104
116
117
100
TA
118
Data
In
119
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.



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