DSP56321 datasheet(46/84 Pages) FREESCALE

номер детали	DSP56321

подробное описание детали	24-Bit Digital Signal Processor

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DSP56321 Technical Data, Rev. 11

2-26

Freescale Semiconductor

Specifications

2.4.9

Timer Timing

Figure 2-25.

ESSI Receiver Timing

Table 2-13.

Timer Timings

No.

Characteristics

Expression

200 MHz

220 MHz

240 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

480

TIO Low

× TC + 2.0

12.0

—

11.1

—

10.3

—

9.27

—

481

TIO High

× TC + 2.0

12.0

—

11.1

—

10.3

—

9.27

—

486

Synchronous delay time from Timer input

rising edge to the external memory

address out valid caused by the first

interrupt instruction execution

10.25

× T

C + 10.0

61.2

—56.6

—52.7

—47.2

—ns

Notes:

VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF

The maximum frequency of pulses generated by a timer will be defined after device characterization is completed.

In the timing diagrams below, TIO is drawn using the rising edge as the reference. TIO polarity is programmable in the Timer

Control/Status Register (TCSR). Refer to the

DSP56321 Reference Manual for details.

Last Bit

First Bit

430

432

433

437

438

440

439

443

441

442

443

445

444

431

434

RXC

(Input/

Output)

FSR (Bit)

Out

FSR

(Word)

Out

Data In

FSR (Bit)

FSR

(Word)

Flags In

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