TMPR4938 datasheet(12/716 Pages) TOSHIBA

12 / 716 page

Table of Contents

viii

15.4.14

Interrupt Pending Register (IRPND) 0xF680 .................................................................................. 15-34

15.4.15

Interrupt Current Status Register (IRCS) 0xF6A0........................................................................... 15-37

15.4.16

Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 ................................................................... 15-39

15.4.17

Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 ................................................................... 15-40

15.4.18

Interrupt Request Polarity Control Register (IRPOL) 0xF518 ........................................................ 15-41

15.4.19

Interrupt Request Control Register (IRRCNT) 0xF51C .................................................................. 15-42

15.4.20

Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 .................................. 15-43

15.4.21

Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524 ................................ 15-44

16. Ethernet Controller ............................................................................................................................................... 16-1

16.1

Features ........................................................................................................................................................ 16-1

16.2

Block diagram.............................................................................................................................................. 16-1

16.3

Detailed explanation .................................................................................................................................... 16-2

16.3.1

Accessing the Ethernet Controller ..................................................................................................... 16-2

16.3.2

Data structure..................................................................................................................................... 16-4

16.3.3

System control model ........................................................................................................................ 16-5

16.3.4

Functional overview .......................................................................................................................... 16-6

16.3.5

DMA function block ........................................................................................................................ 16-10

16.3.6

MAC function blocks .......................................................................................................................16-11

16.3.7

Memory configuration ..................................................................................................................... 16-13

16.3.8

MAC operation ................................................................................................................................ 16-20

16.3.9

DMA operation ................................................................................................................................ 16-32

16.4

Registers..................................................................................................................................................... 16-37

16.4.1

Overview ......................................................................................................................................... 16-37

16.4.2

PCI Configuration Register group ................................................................................................... 16-42

16.4.3

DMA Control, Status Register group ............................................................................................... 16-54

16.4.4

Flow Control Register group ........................................................................................................... 16-68

16.4.5

MAC Control, Status Register group ............................................................................................... 16-70

17. SPI (Serial Peripheral Interface) Module (SPI) .................................................................................................... 17-1

17.1

Characteristics.............................................................................................................................................. 17-1

17.2

Block diagram.............................................................................................................................................. 17-2

17.3

Operational description ................................................................................................................................ 17-3

17.3.1

Operation modes ................................................................................................................................ 17-3

17.3.2

Transmitter/Receiver.......................................................................................................................... 17-3

17.3.3

Baud Rate Generator.......................................................................................................................... 17-4

17.3.4

Transfer format .................................................................................................................................. 17-5

17.3.5

Interframe Delay Time Counter ......................................................................................................... 17-6

17.3.6

Buffer configuration .......................................................................................................................... 17-7

17.3.7

SPI system errors ............................................................................................................................... 17-7

17.3.8

Interrupts............................................................................................................................................ 17-7

17.4

Registers....................................................................................................................................................... 17-8

17.4.1

SPI Master Control Register (SPMCR) 0xF800 ................................................................................ 17-8

17.4.2

SPI Control Register 0 (SPCR0) 0xF804..........................................................................................17-9

17.4.3

SPI Control Register 1 (SPCR1) 0xF808..........................................................................................17-11

17.4.4

SPI Interframe Delay Time Counter (SPFS) 0xF80C ...................................................................... 17-12

17.4.5

SPI Status Register (SPSR) 0xF814................................................................................................ 17-13

17.4.6

SPI Data Register (SPDR) 0xF818 ................................................................................................. 17-14

18. NAND Flash Memory IPL ................................................................................................................................... 18-1

18.1

Features ........................................................................................................................................................ 18-1

18.2

Block Diagram ............................................................................................................................................. 18-2

18.2.1

System Block Diagram ...................................................................................................................... 18-2

18.2.2

Function Block Diagram.................................................................................................................... 18-2

18.3

Detailed Explanation.................................................................................................................................... 18-3

18.3.1

NAND IPL Operation Conditions...................................................................................................... 18-3

18.3.2

NAND IPL Operation ........................................................................................................................ 18-4

18.3.3

NAND Flash Memory IPL Address Map........................................................................................... 18-8

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