TMPR4938 datasheet(5/716 Pages) TOSHIBA

5 / 716 page

Table of Contents

Handling Precautions

TMPR4938

1. Overview and Features ........................................................................................................................................... 1-1

1.1

Overview........................................................................................................................................................ 1-1

1.2

Features .......................................................................................................................................................... 1-1

1.2.1

Features of the TX49/H3 core.............................................................................................................. 1-2

1.2.2

Features of TX4938 peripheral functions ............................................................................................ 1-2

2. Configuration.......................................................................................................................................................... 2-1

2.1

TX4938 block diagram .................................................................................................................................. 2-1

3. Signals

............................................................................................................................................................. 3-1

3.1

Pin Signal Description ................................................................................................................................... 3-1

3.1.1

Signals Common to SDRAM and External Bus Interfaces.................................................................. 3-1

3.1.2

SDRAM Interface Signals ................................................................................................................... 3-2

3.1.3

External Interface Signals .................................................................................................................... 3-3

3.1.4

DMA Interface Signals ........................................................................................................................ 3-4

3.1.5

PCI Interface Signals ........................................................................................................................... 3-4

3.1.6

Serial I/O Interface Signals.................................................................................................................. 3-6

3.1.7

Timer Interface Signals........................................................................................................................ 3-6

3.1.8

Parallel I/O Interface Signals ............................................................................................................... 3-6

3.1.9

AC-link Interface Signals .................................................................................................................... 3-7

3.1.10

Interrupt Signals................................................................................................................................... 3-7

3.1.11

SPI Interface Signals............................................................................................................................ 3-7

3.1.12

ISA/ATA Interface Signals................................................................................................................... 3-8

3.1.13

ETHER Interface Signals (Channel 0)................................................................................................. 3-8

3.1.14

ETHER Interface Signals (Channel 1)................................................................................................. 3-9

3.1.15

NAND Flash Memory Interface Signals............................................................................................ 3-10

3.1.16

Extended EJTAG Interface Signals.................................................................................................... 3-10

3.1.17

Clock Signals ..................................................................................................................................... 3-11

3.1.18

Initialization Signal............................................................................................................................ 3-11

3.1.19

Test Signals ........................................................................................................................................ 3-11

3.1.20

Power Supply Pins ............................................................................................................................. 3-12

3.2

Boot Configuration ...................................................................................................................................... 3-13

3.3

Pin multiplex................................................................................................................................................ 3-17

4. Address Mapping.................................................................................................................................................... 4-1

4.1

TX4938 Physical Address Map...................................................................................................................... 4-1

4.2

Register Map.................................................................................................................................................. 4-2

4.2.1

Addressing ........................................................................................................................................... 4-2

4.2.2

Ways to Access to Internal Registers ................................................................................................... 4-2

4.2.3

Register Map........................................................................................................................................ 4-3

5. Configuration Registers .......................................................................................................................................... 5-1

5.1

Detailed Description ...................................................................................................................................... 5-1

5.1.1

Detecting G-Bus Timeout .................................................................................................................... 5-1

5.2

Registers......................................................................................................................................................... 5-2

5.2.1

Chip Configuration Register (CCFG) 0xE000..................................................................................... 5-3

5.2.2

Chip Revision ID Register (REVID) 0xE008...................................................................................... 5-6

5.2.3

Pin Configuration Register (PCFG) 0xE010 ....................................................................................... 5-7

5.2.4

Timeout Error Access Address Register (TOEA) 0xE018 ................................................................ 5-10

5.2.5

Clock Control Register (CLKCTR) 0xE020...................................................................................... 5-11

5.2.6

G-Bus Arbiter Control Register (GARBC) 0xE030........................................................................... 5-14

5.2.7

Register Address Mapping Register (RAMP) 0xE048 ...................................................................... 5-15

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