TMPR4938 datasheet(96/716 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-8

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

DRVDATA

DATA Signal

Control

Specifies the driving capability of the DATA[63:0] signals.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[4]

R/W

DRVCB

CB Signal

Control

Specifies the driving capability of the CB[7:0]* signals.

L : 0 = 8 mA

H : 1 = 16 mA

Note: CB[7:0]* share pins with PIO[15:8], E0TXD[3:0],

E0RXD[3:0].

The driving capability of these pins are below.

CB[7:0], E0TXD[3:0], E0RXD[3:0]: 8 mA or 16 mA

PIO[15:8]: 8 mA only

ADDR[4]

R/W

DRVDQM

DQM Signal

Control

Specifies the driving capability of the DQM[7:0]* signals.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[4]

R/W

DRVADDR

ADDR Signal

Control

Specifies the driving capability of the ADDR[19:0] signals.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

DRVCKE

CKE Signal

Control

Specifies the driving capability of the CKE signal.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

DRVRAS

RAS Signal

Control

Specifies the driving capability of the RAS* signal.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

DRVCAS

CAS Signal

Control

Specifies the driving capability of the CAS* signal.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

DRVWE

WE Signal

Control

Specifies the driving capability of the WE* signal.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

48:45

DRVCS[3:0]

SDRAM CS

Signal Control

Specifies the driving capability of the SDCS[3:0]* signals.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

44:41

DRVCK[3:0]

SDRAM SDCLK

Signal Control

Specifies the driving capability of the SDCLK[3:0] signals.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

DRVCKIN

SDRAM

SDCLKIN

Signal Control

Specifies the driving capability of the SDCLKIN signal.

L : 0 = 8 mA

H : 1 = 16 mA

ADDR[5]

R/W

39:33

⎯

Reserved

⎯

BYPASS PLL Bypass PLL

Indicates information about whether a PLL for a circuit other

than the PCI controller is on or off.

L: 0 = The PLL is off.

H: 1 = The PLL is on.

BYPASSPLL* R

31:30

⎯

Reserved

⎯

29:28

SDCLKDLY

SDCLK

Feedback Delay

Specifies the feedback delay for the SDCLK. This function is

for diagnosis purposes. Usually, set the bits to 00.

00 = Delay 1 (minimum delay)

10 = Delay 2

01 = Delay 3

11 = Delay 4 (maximum delay)

R/W

SYSCLKEN

SYSCLK Enable Specifies whether to output the SYSCLK.

1 = Clock output

0 = H

R/W

Figure 5.2.3 Pin Configuration Register (2/3)

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