TMPR4938 datasheet(7/716 Pages) TOSHIBA

7 / 716 page

Table of Contents

iii

8.3.15

Restrictions in Access to PCI Bus...................................................................................................... 8-22

8.4

DMA Controller Registers ........................................................................................................................... 8-23

8.4.1

DMA Master Control Register (DM0MCR, DM1MCR)................................................................... 8-25

8.4.2

DMA Channel Control Register (DM0CCRn, DM1CCRn) .............................................................. 8-27

8.4.3

DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................ 8-31

8.4.4

DMA Source Address Register (DM0SARn, DM1SARn) ................................................................ 8-33

8.4.5

DMA Destination Address Register (DM0DARn, DM1DARn)........................................................ 8-34

8.4.6

DMA Chain Address Register (DM0CHARn, DM1CHARn) ........................................................... 8-35

8.4.7

DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)............................................. 8-36

8.4.8

DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) .................................... 8-37

8.4.9

DMA Count Register (DM0CNTRn, DM1CNTRn).......................................................................... 8-38

8.4.10

DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ........................................................ 8-39

8.5

Timing Diagrams ......................................................................................................................................... 8-40

8.5.1

Single Address Single Transfer from Memory to I/O (32-bit ROM) ................................................. 8-40

8.5.2

Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-41

8.5.3

Single Address Single Transfer from I/O to Memory (32-bit SRAM)............................................... 8-42

8.5.4

Single Address Burst Transfer from Memory to I/O (32-bit ROM) .................................................. 8-43

8.5.5

Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ................................................ 8-44

8.5.6

Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-46

8.5.7

Single Address Single Transfer from I/O to Memory (16-bit SRAM)............................................... 8-47

8.5.8

Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) .............................. 8-48

8.5.9

Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) ............................ 8-49

8.5.10

Single Address Single Transfer from Memory to I/O (64-bit SRAM)............................................... 8-50

8.5.11

Single Address Single Transfer from I/O to Memory (64-bit SDRAM) ............................................ 8-51

8.5.12

Single Address Single Transfer from Memory to I/O of Last Cycle

when DMADONE* Signal is Set to Output ...................................................................................... 8-52

8.5.13

Single Address Single Transfer from Memory to I/O (32-bit SDRAM) ............................................ 8-53

8.5.14

Single Address Single Transfer from I/O to Memory (32-bit SDRAM) ............................................ 8-54

8.5.15

External I/O Device – SRAM Dual Address Transfer ....................................................................... 8-55

8.5.16

External I/O Device – SDRAM Dual Address Transfer .................................................................... 8-57

8.5.17

External I/O Device (Non-burst) – SDRAM Dual Address Transfer................................................. 8-59

9. SDRAM Controller................................................................................................................................................. 9-1

9.1

Characteristics................................................................................................................................................ 9-1

9.2

Block Diagram ............................................................................................................................................... 9-2

9.3

Detailed Explanation...................................................................................................................................... 9-3

9.3.1

Supported SDRAM configurations...................................................................................................... 9-3

9.3.2

Address Mapping................................................................................................................................. 9-4

9.3.3

Initialization of SDRAM ..................................................................................................................... 9-9

9.3.4

Initialization of Memory Data, ECC/Parity .......................................................................................9-10

9.3.5

Low Power Consumption Function ................................................................................................... 9-11

9.3.6

Bus Errors .......................................................................................................................................... 9-12

9.3.7

Memory Read and Memory Write ..................................................................................................... 9-12

9.3.8

Slow Write Burst................................................................................................................................ 9-12

9.3.9

Clock Feedback ................................................................................................................................. 9-12

9.3.10

ECC ................................................................................................................................................... 9-13

9.4

Registers....................................................................................................................................................... 9-17

9.4.1

SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1)

0x8010 (ch. 2) 0x8018 (ch. 3)........................................................................................................... 9-18

9.4.2

SDRAM Timing Register (SDCTR) 0x8040 ..................................................................................... 9-20

9.4.3

SDRAM Command Register (SDCCMD) 0x8058 ............................................................................ 9-22

9.4.4

ECC Control Register (ECCCR) 0xA000.......................................................................................... 9-23

9.4.5

ECC Status Register (ECCSR) 0xA008............................................................................................. 9-25

9.5

Timing Diagrams ......................................................................................................................................... 9-26

9.5.1

Single Read (64-bit Bus).................................................................................................................... 9-26

9.5.2

Single Write (64-bit Bus) ................................................................................................................... 9-28

9.5.3

Burst Read (64-bit Bus) ..................................................................................................................... 9-30

9.5.4

Burst Write (64-bit Bus) .................................................................................................................... 9-31

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