TMPR4938 datasheet(92/716 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-4

Bit

Mnemonic Field Name

Description

Initial Value Read/Write

PCI66

PCI 66MHz

Mode

Used to inform the device connected to the PCI bus that a 66

MHz operation is to be performed. This bit is valid only when the

PCI controller of the TX4938 is in host mode. (Refer to Section

10.3.8.)

0 = Do not perform a 66 MHz operation.

1 = Perform a 66 MHz operation.

R/W

PCIMODE

PCI

Operation

Mode

Indicates information about the operation mode of the TX4938

PCI controller. (Refer to Section 10.3.1.)

L: 0: Satellite mode

H: 1: Host mode

ADDR[19]

PCI1-66

PCI1 66MHz

Mode

Used to inform the ETHERC0 and ETHERC1 connected to the

PCI1 bus that a 66 MHz operation is to be performed.

0 = Do not perform a 66 MHz operation (1/4 GBUSCLK).

1 = Perform a 66 MHz operation (1/2 GBUSCLK).

R/W

20:17

DIVMODE

CPUCLK

Frequency

Multiplication

Factor

Indicates information about the frequency multiplication factor of

the TX49/H3 core clock (CPUCLK) to the MASTERCLK. This

field is set with a result of encoding an initial input value at

ADDR[3:0].

The PLL incorporated in the TX4938 multiplies the

MASTERCLK and supplies the resulting frequency to the

TX49/H3 core.

The value set in DIVMODE[3:0] is reflected in the EC field of the

TX49/H3 core Config register.

ADDR[3:0]:DIVMODE[3:0]

HHHH: 0100: CPUCLK freq.

= 2 × MASTERCLK freq.

HHHL: 1111: CPUCLK freq.

= 2.5 × MASTERCLK freq.

HHLH: 0101: CPUCLK freq.

= 3 × MASTERCLK freq.

HHLL: 0110: CPUCLK freq.

= 4 × MASTERCLK freq.

LHHH: 1101: CPUCLK freq. = 4.5 x MASTERCLK freq.

LHHL: ---- : Reserved

LHLH: ---- : Reserved

LHLL: ---- : Reserved

HLHH: 0000: CPUCLK freq.

= 8 × MASTERCLK freq.

HLHL: 1011: CPUCLK freq.

= 10 × MASTERCLK freq.

HLLH: 0001: CPUCLK freq.

= 12 × MASTERCLK freq.

HLLL: 0010: CPUCLK freq.

= 16 × MASTERCLK freq.

LLHH: 1001: CPUCLK freq.

= 18 × MASTERCLK freq.

LLHL: ---- : Reserved

LLLH: ---- : Reserved

LLLL: ---- : Reserved

ADDR[3:0]

BEOW

Write-Access

Bus Error

Indicates that a timeout error has occurred in the internal bus (G-

Bus) during a write bus transaction of the TX49/H3 core. This bit

corresponds to interrupt No. 1 in the interrupt controller.

0 = No error has occurred.

1 = An error has occurred.

R/W1C

Watchdog

Timer Mode

Specifies how information will be reported in watchdog timer

mode (refer to Section 12.3.6).

0 = Generate an NMI exception.

1 = Generate a watchdog reset.

R/W

TOE

G-Bus

Timeout

Error

Detection

Specifies whether to detect and report a bus timeout error in the

internal bus (G-Bus) of the TX4938.

0 = Do not detect or report a bus timeout error.

1 = Detect and report a bus timeout error.

R/W

PCIARB

PCI Arbiter

Selection

Indicates the PCI bus arbiter selection setting (refer to Section

10.3.12).

L: 0 = External PCI bus arbiter

H: 1 = Built-in PCI bus arbiter

DATA[2]

Figure 5.2.1 Chip Configuration Register (2/3)

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