TMPR4938 datasheet(97/716 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-9

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

26:23 SDCLKEN [3:0] SDCLK Enable Individually specifies whether to output each of SDCLK[3:0].

1 = Clock output

0 = H

Bit 26 = SDCLK[3]

Bit 25 = SDCLK[2]

Bit 24 = SDCLK[1]

Bit 23 = SDCLK[0]

1111

R/W

SDCLKINEN

SDCLKIN

Enable

Specifies how SDCLK[3:0] should be fed back. This function

is for diagnosis purposes. Usually, set this bit to 0.

0 = Use the SDCLKIN signal as a feedback clock.

1 = Perform feedback within the TX4938 (the SDCLKIN

becomes an output signal).

R/W

21:16 PCICLKEN [5:0] PCICLK Enable Individually specifies whether to output each of PCICLK[5:0].

1 = Clock output

0 = H

Bit 21 = PCICLK[5]

Bit 20 = PCICLK[4]

Bit 19 = PCICLK[3]

Bit 18 = PCICLK[2]

Bit 17 = PCICLK[1]

Bit 16 = PCICLK[0]

111111

R/W

15:10

⎯

Reserved

⎯

SEL2

Shared-Pin

Status 2

DMAREQ[2], DMAACK[2], and PIO[4:2] share pins with the

AC-link interface signals. Indicates which function the shared

pins are set to.

L: 0 = The shared pins are set to DMAREQ[2], DMAACK[2],

and PIO[4:2].

H: 1 = The shared pins are set to the AC-link interface signals.

ADDR[9]

SEL1

Shared-Pin

Status 1

Indicates which function, PIO[15:8] or CB[7:0], the shared pins

are set to.

L: 0 = The shared pins are set to PIO[15:8].

H: 1 = The shared pins are set to CB[7:0].

ADDR[18]

7:4

⎯

Reserved

⎯

DMASEL3

DMA Request

Select 3

Selects a DMA request used by DMA controller 0 channel 3.

0: DMAREQ[3] (external)

1: SIO channel 0 transmission (internal)

R/W

DMASEL2

DMA Request

Select 2

Selects a DMA request used by DMA controller 0 channel 2.

0: DMAREQ[2] (external)

1: SIO channel 0 reception (internal)

R/W

DMASEL1

DMA Request

Select 1

Selects a DMA request used by DMA controller 0 channel 1.

00: DMAREQ[1] (external)

01: SIO channel 1 transmission (internal)

R/W

1:0

DMASEL0

DMA Request

Select 0

Selects a DMA request used by DMA controller 0 channel 0.

00: DMAREQ[0] (external)

01: SIO channel 1 reception (internal)

R/W

Figure 5.2.3 Pin Configuration Register (3/3)

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