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ELANSC310 датащи(PDF) 106 Page - Advanced Micro Devices

номер детали ELANSC310
подробное описание детали  Single-Chip, 32-Bit, PC/AT Microcontroller
PDF  119 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
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ELANSC310 датащи(HTML) 106 Page - Advanced Micro Devices

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106
Élan™SC310 Microcontroller Data Sheet
PREL IMINARY
Notes:
These timings are based on default settings and required initial programming. These timings may be modified via the MMS
Memory Wait State1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ÉlanTMSC310 Microcontroller
Programmer’s Reference Manual
, order #20665.)
Table 55.
ISA Memory Read/Write 8-Bit Cycle (See Figure 44)
Symbol
Parameter Description
Notes
Preliminary
Units
Min
Max
t1
LA stable to BALE inactive
60
ns
t2
SA stable to command active
160
ns
t3
BALE pulse width
35
ns
t4
LA hold from BALE inactive
40
ns
t5a
SA hold from command inactive Write
50
ns
t5b
SA hold from command inactive Read
0
ns
t6
BALE inactive to command active
140
ns
t7a
MEMW command pulse width
500
ns
t7b
MEMR command pulse width
550
ns
t8a
MEMW active to IOCHRDY inactive
340
ns
t8b
MEMR active to IOCHRDY inactive
340
ns
t9a
MEMW hold from IOCHRDY active
110
ns
t9b
MEMR hold from IOCHRDY active
160
ns
t10
RDDATA setup to command inactive
40
ns
t11
RDDATA hold from command inactive
0
ns
t12
WRDATA setup to command inactive
300
ns
t13
WRDATA hold from command inactive
50
ns
t14
DBUFOE active from command
5
ns
t15a
DBUFOE hold from MEMW
50
ns
t15b
DBUFOE hold from MEMR
–2
ns
t16
ENDIRH, ENDIRL setup to MEMR
170
ns
t17
ENDIRH, ENDIRL hold from MEMR
–4
ns
t18
LA stable to SA stable
15
ns
t19
SA stable to BALE inactive
45
ns



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