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SC486

POWER MANAGEMENT

Layout Guidelines (Cont.)

Key points for the switcher power section:

1) there should be a very small input loop, well decoupled.

2) the phase node should be a large copper pour, but compact since this is the noisiest node.

3) input power ground and output power ground should not connect directly, but through the ground planes instead.

Connecting the control and switcher power sections should be accomplished as follows (see Figure 12 below):

1) Route VDDQ feedback trace in a “quiet” layer away from noise sources.

2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces

with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization,

with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power

ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies,

thus should be kept as short as practical. DH has LX as its return path.

3) BST is also a noisy node and should be kept as short as possible.

4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the

ground plane.

R10 13k0

L1

1u5

PGND1

18

REF

8

EN/PSV

1

TON

2

VDDQS

3

VCCA

5

FB

6

PGD

7

VSSA

4

PGND2

17

DL

19

VDDP

20

ILIM

21

LX

22

DH

23

BST

24

VTTEN

11

VTT

15

PGND2

16

VTTIN

12

VTTIN

13

VTT

14

VTTS

10

COMP

9

PAD

U1

SC486

Q1

IRF7811AV

Q2

FDS6676S

Figure 12: Connecting Control and Switcher Power Sections

Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node

traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical. Use multiple

vias when switching between layers. Locate the current limit resistor (R10) at the chip with a kelvin connection to

the phase node.