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SC486 датащи(PDF) 16 Page - Semtech Corporation

номер детали SC486
подробное описание детали  Complete DDR1/2/3 Memory Power Supply
PDF  26 Pages
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производитель  SEMTECH [Semtech Corporation]
домашняя страница  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC486 датащи(HTML) 16 Page - Semtech Corporation

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 2006 Semtech Corp.
www.semtech.com
SC486
POWER MANAGEMENT
Design Procedure (Cont.)
For our DDR2 VDDQ example:
I
RIPPLE_VBAT(MIN) = 2.62AP-P and IRIPPLE_VBAT(MAX) = 3.28AP-P
From this we can calculate the minimum inductor
current rating for normal operation:
)
MIN
(
)
MAX
(
VBAT
_
RIPPLE
)
MAX
(
OUT
)
MIN
(
INDUCTOR
A
2
I
I
I
+
=
For our DDR2 VDDQ example:
I
INDUCTOR(MIN) = 11.6A(MIN)
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R
ESR_ST(MAX)) and transient ESR
(R
ESR_TR(MAX)):
()
Ohms
I
2
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
DC
ST
)
MAX
(
ST
_
ESR
•
−
=
Where ERR
ST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
feedback resistors.
For our DDR2 VDDQ example:
ERR
ST = 72mV and ERRDC = 36mV, therefore
R
ESR_ST(MAX) = 22mΩ
()
Ohms
2
I
I
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
OUT
DC
TR
)
MAX
(
TR
_
ESR


+
−
=
Where ERR
TR is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the I
OUT
term by 2.
For our DDR2 VDDQ example:
ERR
TR = 100mV and ERRDC = 36mV, therefore
R
ESR_TR(MAX) = 5.5mΩ for a full 10A load transient
We will select a value of 7.5m
Ω maximum for our
design, which would be achieved by using two 15m
Ω
output capacitors in parallel.
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
SW
OUT
)
MIN
(
ESR
f
C
2
3
R
•
•
π
•
=
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
P
P
)
MAX
(
VBAT
_
RIPPLE
ESR
)
MAX
(
VBAT
_
RIPPLE
V
I
R
V
−
•
=
and
P
P
)
MIN
(
VBAT
_
RIPPLE
ESR
)
MIN
(
VBAT
_
RIPPLE
V
I
R
V
−
•
=
For our DDR2 VDDQ example:
V
RIPPLE_VBAT(MAX) = 25mVP-P and VRIPPLE_VBAT(MIN) = 20mVP-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V
FB, should be approximately 15mVP-P at minimum
V
BAT, and wo rst case no smaller than 10mVP-P. If
V
RIPPLE_VBAT(MIN) is less than 15mVP-P the above component
values should be revisited in order to improve this. A small
capacitor, C
TOP, may be required in parallel with the top
feedback resistor, R
TOP, in order to ensure that VFB is large
enough. C
TOP should not be greater than 100pF. The value
of C
TOP can be calculated as follows, where RBOT is the
bottom feedback resistor. Firstly calculating the value of
Z
TOP required:
()Ohms
015
.
0
V
015
.
0
R
Z
)
MIN
(
VBAT
_
RIPPLE
BOT
TOP
−
•
=



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