HT45R34 datasheet(14/41 Pages) HOLTEK

14 / 41 page

HT45R34

Rev. 1.20

October 15, 2007

The TM0, TM1 bits define the operating mode. The event

count mode is used to count external events, which

means the clock source comes from an external TMR

pin. The timer mode functions as a normal timer with the

clock source coming from the fINT clock. The pulse width

measurement mode can be used to measure the high or

low level duration of an external signal on the TMR pin.

The counting is based on the fINT clock source. In the

event counting or timer mode, once the timer/event coun-

ter starts counting, it will count from the current contents

in the Timer/Event Counter to FFH. Once overflow oc-

curs, the counter is reloaded from the Timer/Event Coun-

ter preload register and an interrupt request flag TF; bit 5

of INTC0, is generated at the same time.

In the pulse width measurement mode, with the TON

and TE bits equal to one, once the TMR pin has re-

ceived a transient from low to high, or high to low if the

TE bit is 0, it will start counting until the TMR pin returns

to its original level and resets the TON bit. The mea-

sured result will remain in the Timer/Event Counter even

if the activated transient occurs again. Therefore, only a

single shot measurement can be made. The TON bit

must be set again by software for further measurements

to be made. Note that, in this operating mode, the

Timer/Event Counter starts counting not according to

the logic level but according to the transient edges. In

the case of a counter overflow, the counter is reloaded

from the Timer/Event Counter preload register and is-

sues an interrupt request just like the other two modes.

To enable a counting operation, the Timer ON bit, TON; bit

4 of TMRC, should be set to

²1². In the pulse width mea-

surement mode, the TON will be cleared automatically af-

ter the measurement cycle is completed. But in the other

two modes, the TON can only be reset by instructions. The

Timer/Event Counter overflow is one of the wake-up

sources. No matter what the operation mode is, writing a 0

to ETI can disable the interrupt service.

If the Timer/Event Counter is switched off, then writing

data to the Timer/Event Counter preload register will

also directly reload that data to the Timer/Event Coun-

ter. But if the Timer/Event Counter is already running,

data written to it will only be loaded into the Timer/Event

Counter preload register. The Timer/Event Counter will

continue to operate until an overflow occurs. When the

Timer/Event Counter is read, the clock will be blocked to

avoid errors. As clock blocking may results in a counting

error, this must be taken into consideration by the pro-

grammer. Bit0~Bit2 of the TMRC register can be used to

define the pre-scaling stages of the internal clock source

of the Timer/Event Counter.

External RC Oscillation Converter

An external RC oscillation mode is implemented in the

device. The RC oscillation converter contains two 16-bit

programmable count-up counters.

The RC oscillation converter is comprised of the

TMRAL, TMRAH, TMRBL, TMRBH registers when the

RCO bit, bit 1 of RCOCR register, is

²1². The RC oscilla-

tion converter Timer B clock source may come from an

external RC oscillator. The Timer A clock source comes

from the system clock or from the system clock/4, deter-

mined by the RCOCCR register.

There are six registers related to the RC oscillation con-

verter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH,

TMRBL and RCOCR. The internal timer clock is the in-

put to TMRAH and TMRAL, the external RC oscillation

is the input to TMRBH and TMRBL. The OVB bit, bit 0 of

the RCOCR register, decides whether Timer A over-

flows or Timer B overflows, then the RCOCF bit is set

and an external RC oscillation converter interrupt oc-

curs. When the RC oscillation converter mode Timer A

or Timer B overflows, the RCOCON bit is reset to

²0²

and stops counting. Writing to TMRAH/TMRBH places

the start value in Timer A/Timer B while reading

TMRAH/TMRBH obtains the contents of Timer A/Timer

B. Writing to TMRAL/TMRBL only writes the data into a

low byte buffer. However writing to TMRAH/TMRBH will

write the data and the contents of the low byte buffer into

the Timer A/Timer B (16-bit) simultaneously. Timer

A/Timer B is changed by writing to TMRAH/TMRBH but

writing to TMRAL/TMRBL will keep the Timer A/Timer B

unchanged.

Reading TMRAH/TMRBH will also latch the

TMRAL/TMRBL into the low byte buffer to avoid false

timing problem. Reading TMRAL/TMRBL returns the

contents of the low byte buffer. Therefore, the low byte

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - B i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

8 - B i t T i m e r / E v e n t

C o u n t e r ( T M R )

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

7 - S t a g e P r e s c a l e r

8 - 1 M U X

f I N T

T P S C 2 ~ T P S C 0

S y s t e m C l o c k

Timer/Event Counter

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