HT45R34 datasheet(10/41 Pages) HOLTEK

10 / 41 page

HT45R34

Rev. 1.20

October 15, 2007

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

Both are designed for system clocks, namely the RC os-

cillator and the Crystal oscillator, the choice of which is

determined by a configuration option. When the device

enters the Power-down Mode, the system oscillator will

stop running and will ignore external signals to conserve

power.

If an RC oscillator is used, an external resistor between

OSC1 and VDD is required to produce oscillation. The

resistance must range from 24k

W to 1MW. The system

clock, divided by 4, is available on OSC2, which can be

used to synchronize external logic. The RC oscillator

provides the most cost effective solution, however, the

frequency of oscillation may vary with VDD, tempera-

tures and the device itself due to process variations. It is,

therefore, not suitable for timing sensitive operations

where an accurate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator. No other external compo-

nents are required. Instead of a crystal, a resonator can

also be connected between OSC1 and OSC2 to get a

frequency reference, but two external capacitors con-

nected between OSC1, OSC2 and ground are required,

if the oscillator frequency is less than 1MHz.

The WDT oscillator is a free running on-chip RC oscilla-

tor which requires no external components. Even if the

system enters the Power Down Mode, where the sys-

tem clock is stopped, the WDT oscillator will continue to

operate with a period of approximately 65

msat5V.The

WDT oscillator can be disabled by a configuration option

to conserve power.

Watchdog Timer

- WDT

The WDT clock can be sourced from its own dedicated

internal oscillator (WDT oscillator), or from the or in-

struction clock, which is the system clock divided by 4.

The choice is determined via a configuration option. The

WDT timer is designed to prevent a software malfunc-

tion or sequence from jumping to an unknown location

with unpredictable results. The Watchdog Timer can be

disabled by a configuration option. If the Watchdog

Timer is disabled, any executions related to the WDT re-

sult in no operation.

The WDT clock source is first divided by 256. If the inter-

nal WDT oscillator is used ,this gives a nominal time-out

period of approximately 17ms at 5V. This time-out pe-

riod may vary with temperatures, VDD and process vari-

ations. By using the WDT prescaler, longer time-out

periods can be realised. Writing data to the WS2, WS1,

WS0 bits in the WDTS register, can give different

time-out periods. If WS2, WS1 and WS0 are all equal to

1, the division ratio will be 1:128, and the maximum

time-out period will be 2.1s at 5V. If the internal WDT os-

cillator is disabled, the WDT clock may still come from

the instruction clock and operate in the same manner

except that in the Power Down state the WDT will stop

counting and lose its protecting purpose. The high nib-

ble and bit 3 of the WDTS can be used for user defined

flags.

If the device operates in a noisy environment, using the

internal WDT oscillator is the recommended choice,

since the HALT instruction will stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

The WDT overflow under normal operation will generate

²chip reset² and set the status bit ²TO². But in the

Power Down mode, the overflow will generate a

²warm

reset

², where only the Program Counter and Stack

Pointer are reset to zero. To clear the contents of the

WDT, including the WDT prescaler, three methods can

be used; an external reset (a low level to RES), a soft-

ware instruction and a

²HALT² instruction. The software

instruction includes

²CLR WDT² instruction and the in-

struction pair

-²CLR WDT1² and ²CLR WDT2².Of

these two types of instruction, only one can be active de-

pending on the configuration option

-²CLR WDT times

selection option

².Ifthe ²CLR WDT² is selected, i.e.

CLRWDT times equal one, any execution of the

²CLR

WDT

² instruction will clear the WDT. In the case that

²CLR WDT1² and ²CLR WDT2² are chosen, i.e.

CLRWDT times equal two, these two instructions must

be executed to clear the WDT; otherwise, the WDT may

reset the chip as a result of a time-out.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

N M O S O p e n D r a i n

O S C 2

f S Y S / 4

4 7 0 p F

V D D

O S C 1

System Oscillator

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