HT45R34 datasheet(9/41 Pages) HOLTEK

9 / 41 page

HT45R34

Rev. 1.20

October 15, 2007

abled, the stack is not full, and the external interrupt is

active, a subroutine call to location

²04H² or ²08H² will

occur. The interrupt request flags, EIF0 or EIF1, and the

EMI bit will all be cleared to disable other interrupts.

The internal Timer/Event Counter interrupt is initialised

by setting the Timer/Event Counter interrupt request

flag, TF; bit 6 in INTC0. A timer interrupt will be gener-

ated when the timer overflows. After the interrupt is en-

abled, and the stack is not full, and the TF bit is set, a

subroutine call to location

²0CH² will occur. The related

interrupt request flag, TF, is reset, and the EMI bit is

cleared to disable other interrupts.

The external RC oscillation converter interrupt is initial-

ized by setting the external RC oscillation converter in-

terrupt request flag, RCOCF; bit 4 of INTC1. This is

caused by a Timer A or Timer B overflow. When the in-

terrupt is enabled, and the stack is not full and the

RCOCF bit is set, a subroutine call to location

²10H² will

occur. The related interrupt request flag, RCOCF, will be

reset and the EMI bit cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the

²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1, if the stack is not full. To

return from the interrupt subroutine, a

²RET² or ²RETI²

instruction may be invoked. RETI will set the EMI bit to

enable an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External Interrupt 0

04H

External Interrupt 1

08H

Timer/Event Counter Overflow

0CH

External RC Oscillation

Converter Interrupt

10H

Interrupt Priority

The EMI, EEI0, EEI1, ETI and ERCOCI bits are all used

to control the enable/disable status of interrupts. These

bits prevent the requested interrupt from being serviced.

Once the interrupt request flags, TF, RCOCF, EIF1 and

EIF0, are all set, they remain in the INTC1 or INTC0 reg-

isters respectively until the interrupts are serviced or

cleared by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only one

stack is left and enabling the interrupt is not well con-

trolled, the original control sequence may be damaged

once the

²CALL² is executed in the interrupt subroutine.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1= enabled; 0= disabled)

EEI0

Controls the external interrupt 0 (1= enabled; 0= disabled)

EEI1

Controls the external interrupt 1 (1= enabled; 0= disabled)

ETI

Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)

EIF0

External interrupt 0 request flag (1= active; 0= inactive)

EIF1

External interrupt 1 request flag (1= active; 0= inactive)

Internal Timer/Event Counter request flag (1= active; 0= inactive)

Unused bit, read as

²0²

INTC0 (0BH) Register

Bit No.

Label

Function

ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)

1~3, 5~7

Unused bit, read as

²0²

RCOCF

External RC oscillation converter request flag (1= active; 0= inactive)

INTC1 (1EH) Register

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