PM7367 datasheet(145/323 Pages) PMC

145 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

131

XFER[2:0]:

The indirect channel transfer size (XFER[2:0]) configures the amount of data

transferred in each transaction. The channel transfer size to be written to the

channel provision RAM, in an indirect write operation, must be set up in this

the depth specified by XFER[2:0] or when an end-of-packet exists in the

FIFO, a request will be made to the RMAC to initiate a PCI write access to

transfer the data to the PCI host. Channel transfer size is measured in 16

byte blocks. The amount of data transferred and the depth threshold are

specified by given setting is:

XFER[2:0] + 1 blocks = 16 * (XFER[2:0] + 1) bytes

XFER[2:0] should be set such that the number of blocks transferred is at

least two fewer than the total allocated to the associated channel. XFER[2:0]

reflects the value written until the completion of a subsequent indirect channel

read operation.

OFFSET[1:0]:

The packet byte offset (OFFSET[1:0]) configures the partial packet processor

to insert invalid bytes at the beginning of a packet stored in the channel FIFO.

The value of OFFSET[1:0] to be written to the channel provision RAM, in an

indirect channel write operation, must be set up in this register before

triggering the write. The number of bytes inserted before the beginning of a

HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0]

reflects the value written until the completion of a subsequent indirect channel

read operation.

INVERT:

The HDLC data inversion bit (INVERT) configures the HDLC processor to

logically invert the incoming HDLC stream from the RCAS before processing

it. The value of INVERT to be written to the channel provision RAM, in an

indirect channel write operation, must be set up in this register before

triggering the write. When INVERT is set to one, the HDLC stream is logically

inverted before processing. When INVERT is set to zero, the HDLC stream

is not inverted before processing. INVERT reflects the value written until the

completion of a subsequent indirect channel read operation.

PRIORITY:

The channel FIFO priority bit (PRIORITY) informs the partial packet

processor that the channel has precedence over other channels when being

serviced by the RMAC block for transfer to the PCI host. The value of

PRIORITY to be written to the channel provision RAM, in an indirect channel

write operation, must be set up in this register before triggering the write.

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