PM7367 datasheet(146/323 Pages) PMC

номер детали	PM7367

подробное описание детали	FRAME ENGINE AND DATA LINK MANAGER

PDF	323 Pages

Scroll/Zoom	100%

производитель	PMC [PMC-Sierra, Inc]

домашняя страница	http://www.pmc-sierra.com

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146 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

132

Channel FIFOs with PRIORITY set to one are serviced by the RMAC before

channel FIFOs with PRIORITY set to zero. Channels with an HDLC data rate

to FIFO size ratio that is significantly higher than other channels should have

PRIORITY set to one. PRIORITY reflects the value written until the

completion of a subsequent indirect channel read operation.

7BIT:

The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least

significant bit of each octet in the corresponding link RD[n]. The value of

7BIT to be written to the channel provision RAM, in an indirect channel write

operation, must be set up in this register before triggering the write. When

7BIT is set high, the least significant bit (last bit of each octet received), is

ignored. When 7BIT is set low, the entire receive data stream is processed.

7BIT reflects the value written until the completion of a subsequent indirect

channel read operation.

PM7367 датащи(PDF) 146 Page - PMC-Sierra, Inc