PM7367 datasheet(142/323 Pages) PMC

142 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

128

FPTR[8:0]:

The indirect FIFO block pointer (FPTR[8:0]) identifies one of the blocks of the

circular linked list in the partial packet buffer used in the logical FIFO of the

current channel. The FIFO pointer to be written to the channel provision

RAM, in an indirect write operation, must be set up in this register before

triggering the write. The FIFO pointer value can be any one of the blocks

provisioned to form the circular buffer.

TAVAIL:

The indirect transaction available bit (TAVAIL) reports the fill level of the

partial packet buffer used in the logical FIFO of the current channel. TAVAIL

is set high when the FIFO of the current channel contains sufficient data, as

controlled by XFER[2:0], to request a DMA transfer to the host memory.

TAVAIL is set low when the amount of receive data is too small to require a

transfer to host memory. TAVAIL is update by an indirect channel read

operation.

DELIN:

The indirect delineate enable bit (DELIN) configures the HDLC processor to

perform flag sequence delineation and bit de-stuffing on the incoming data

stream. The delineate enable bit to be written to the channel provision RAM,

in an indirect channel write operation, must be set up in this register before

triggering the write. When DELIN is set high, flag sequence delineation and

bit de-stuffing is performed on the incoming data stream. When DELIN is set

low, the HDLC processor does not perform any processing (flag sequence

delineation, bit de-stuffing nor CRC verification) on the incoming stream.

DELIN reflects the value written until the completion of a subsequent indirect

channel read operation.

STRIP:

The indirect frame check sequence discard bit (STRIP) configures the HDLC

processor to remove the CRC from the incoming frame when writing the data

to the channel FIFO. The FCS discard bit to be written to the channel

provision RAM, in an indirect channel write operation, must be set up in this

not equal to "00", the received CRC value is not written to the FIFO. When

STRIP is set low, the received CRC value is written to the FIFO. The bytes in

buffer field of the RPD correctly reflect the presence/absence of CRC bytes in

the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects

the value written until the completion of a subsequent indirect channel read

operation.

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