PM7367 datasheet(302/323 Pages) PMC

302 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

288

During Clock 5, the target places the second data word onto the AD[31:0] bus

and drives TRDYB to indicate to the initiator that the data is valid.

During Clock 6, the initiator latches the second data word and negates IRDYB to

indicate to the target that it is not ready for the next transfer. The target shall

drive the third data word until the initiator accepts it.

During Clock 7, the initiator asserts IRDYB to indicate to the target it is ready for

the third data word. It also negates FRAMEB since this shall be the last transfer.

During Clock 8, the initiator latches in the last word and negates IRDYB. The

target, having seen FRAMEB negated in the last clock cycle, negates TRDYB

and DEVSELB. All of the above signals shall be driven to their inactive state in

this clock cycle, except for FRAMEB which shall be tri-stated. The target shall

stop driving the AD[31:0] bus and the initiator shall stop driving the C/BEB[3:0]

bus; this shall be the turnaround cycle for these signals.

Figure 28 – PCI Read Cycle

PCICLK

FRAMEB

AD[31:0]

C/BEB[3:0]

IRDYB

TRDYB

DEVSELB

Address

Data 1

Data 2

Data 3

Byte Enable

Bus Cmd

A PCI burst write transaction is shown in Figure 29. The cycle is valid for target

and initiator accesses. The target is responsible for incrementing the address for

the duration of the data burst. The 'T' symbol stands for a turn around cycle. A

turn around cycle is required on all signals which can be driven by more than one

agent.

During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also

drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with

the write command (in the above example the command would indicate a burst

write). The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (no

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