PM7367 datasheet(299/323 Pages) PMC

299 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

285

Figure 23 – Channelised T1 Receive Link Timing

RCLK[n]

RD[n]

B7 B8 F B1 B2B3 B4 B5B6 B7B8 B1B2 B3

TS 24

TS 1

TS 2

The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of

a channelised E1 link is shown in Figure 24. The receive data stream is an E1

frame with a singe framing byte (F1 to F8 in Figure 24) followed by octet bound

time-slots 1 to 31. RCLK[n] is held quiescent during the framing byte. The RD[n]

data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the

framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31)

clocked in by the last rising edge of RLCLK[n] before the framing byte is the least

significant bit of time-slot 31. In Figure 24, the quiescent period is shown to be a

low level on RCLK[n]. A high level, effected by extending the high phase of bit

B8 of time-slot TS31, is equally acceptable. In channelised E1 mode, RCLK[n]

can only be gapped during the framing byte. It must be active continuously at

2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the

PROV bit in the corresponding word of the receive channel provision RAM in the

RCAS block to low.

Figure 24 – Channelised E1 Receive Link Timing

RCLK[n]

RD[n]

B6 B7

F1 F2 F3 F4 F5 F6 F7 F8 B1 B2 B3

TS 31

FAS / NFAS

TS 1

B4 B5 B6 B7 B8 B1 B2 B3 B4

TS 2

13.2 Transmit Link Output Timing

The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals

of a unchannelised link is shown in Figure 25. The transmit data is viewed as a

contiguous serial stream. There is no concept of time-slots in an unchannelised

link. Every eight bits are grouped together into a byte with arbitrary byte

alignment. Octet data is transmitted from most significant bit (B1 in Figure 25)

and ending with the least significant bit (B8 in Figure 25). Bits are updated on

the falling edge of TCLK[n]. A transmit link may be stalled by holding the

corresponding TCLK[n] quiescent. In Figure 25, bits B5 and B2 are shown to be

stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure

PM7367 датащи(PDF) 299 Page - PMC-Sierra, Inc

PM7367 датащи(HTML) 299 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL