PM7367 datasheet(301/323 Pages) PMC

301 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

287

TCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot

31, is equally acceptable. In channelised E1 mode, TCLK[n] can only be gapped

during the framing byte. It must be active continuously at 2.048 MHz during all

time-slot bits. Time-slots that are not provisioned to belong to any channel

(PROV bit in the corresponding word of the transmit channel provision RAM in

the TCAS block set low) transmit the contents of the Idle Time-slot Fill Data

Figure 27 – Channelised E1 Transmit Link Timing

TCLK[n]

TD[n]

B6 B7

B2 B3

TS 31

FAS / NFAS

TS 1

B4 B5 B6 B7 B8 B1 B2 B3 B4

TS 2

13.3 PCI Interface

A PCI burst read cycle is shown In Figure 28. The cycle is valid for target and

initiator accesses. The target is responsible for incrementing the address during

the data burst. The 'T' symbol stands for a turn around cycle. A turn around

cycle is required on all signals which can be driven by more than one agent.

During Clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It

also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines

with the read command. In the example below, the command would indicate a

burst read. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode

(i.e. no agent is driving the signals for this clock cycle). This cycle on the PCI

bus is called the address phase.

During Clock 2, the initiator ceases to drive the AD[31:0] bus in order that the

target can drive it in the next cycle. The initiator also drives the C/BEB[3:0] lines

with the byte enables for the read data. IRDYB is driven active by the initiator to

indicate it is ready to accept the data transfer. All subsequent cycles on the PCI

bus are called data phases.

During Clock 3, the target claims the transaction by driving DEVSELB active. It

also places the first data word onto the AD[31:0] bus and drives TRDYB to

indicate to the initiator that the data is valid.

During Clock 4, the initiator latches in the first data word. The target negates

TRDYB to indicate to the initiator that it is not ready to transfer another data

word.

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