PM7367 datasheet(300/323 Pages) PMC

300 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

286

25, the quiescent period is shown to be a low level on TCLK[n]. A high level,

effected by extending the high phase of the previous valid bit, is also acceptable.

Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame

boundaries.

Figure 25 – Unchannelised Transmit Link Timing

TCLK[n]

TD[n]

B1 B2 B3 B4

B7 B8 B1 B2

The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals

of a channelised T1 link is shown in Figure 26. The transmit data stream is a T1

frame with a single framing bit (F in Figure 26) followed by octet bound time-slots

1 to 24. TCLK[n] is held quiescent during the framing bit. The most significant

bit of each time-slot is transmitted first (B1 in Figure 26). The least significant bit

of each time-slot is transmitted last (B8 in Figure 26). The TD[n] bit (B8 of TS24)

before the framing bit is the least significant bit of time-slot 24. In Figure 26, the

quiescent period is shown to be a low level on TCLK[n]. A high level, effected by

extending the high phase of bit B8 of time-slot TS24, is equally acceptable. In

channelised T1 mode, TCLK[n] can only be gapped during the framing bit. It

must be active continuously at 1.544MHz during all time-slot bits. Time-slots that

are not provisioned to belong to any channel (PROV bit in the corresponding

word of the transmit channel provision RAM in the TCAS block set low) transmit

the contents of the Idle Fill Time-slot Data register.

Figure 26 – Channelised T1 Transmit Link Timing

TCLK[n]

TD[n]

B7 B8

B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3

TS 24

TS 1

TS 2

The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals

of a channelised E1 link is shown in Figure 27. The transmit data stream is an

E1 frame with a singe framing byte (FAS/NFAS in Figure 27) followed by octet

bound time-slots 1 to 31. TCLK[n] is held quiescent during the framing byte.

The most significant bit of each time-slot is transmitted first (B1 in Figure 27).

The least significant bit of each time-slot is transmitted last (B8 in Figure 27).

The TD[n] bit (B8 of TS31) before the framing byte is the least significant bit of

time-slot 31. In Figure 27, the quiescent period is shown to be a low level on

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