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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F631 датащи(PDF) 174 Page - Microchip Technology |
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PIC16F631 датащи(HTML) 174 Page - Microchip Technology |
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174 / 294 page  PIC16F631/677/685/687/689/690 DS41262D-page 172 © 2007 Microchip Technology Inc. FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Value on POR, BOR Value on all other Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception. CREN bit RX/DT Write to bit SREN SREN bit RCIF bit (Interrupt) Read RXREG ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TX/CK pin TX/CK pin pin (SCKP = 0) (SCKP = 1) |
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