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PIC16F631 датащи(PDF) 41 Page - Microchip Technology |
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PIC16F631 датащи(HTML) 41 Page - Microchip Technology |
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41 / 294 page ![]() © 2007 Microchip Technology Inc. DS41262D-page 39 PIC16F631/677/685/687/689/690 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE(5) RCIE(3) TXIE(3) SSPIE(4) CCP1IE(2) TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(5) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit(3) 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit(5) 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit(4) 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit(2) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F685/PIC16F690 only. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F687/PIC16F689/PIC16F690 only. 4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. |
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