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FS6500 датащи(PDF) 90 Page - NXP Semiconductors

номер детали FS6500
подробное описание детали  Safety power system basis chip with CAN FD and LIN transceivers
PDF  153 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6500 датащи(HTML) 90 Page - NXP Semiconductors

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NXP Semiconductors
FS6500-FS4500-ASILD
Safety power system basis chip with CAN FD and LIN transceivers
Description
IO_2 wake-up configuration
00
NO wake-up capability
01
Wake-up on rising edge - or high level
10
Wake-up on falling edge - or low level
11
Wake-up on any edge
WU_IO2_1:0
Reset condition Power on reset
Description
IO_3 wake-up configuration
00
NO wake-up capability
01
Wake-up on rising edge - or high level
10
Wake-up on falling edge - or low level
11
Wake-up on any edge
WU_IO3_1:0
Reset condition Power on reset
Description
IO_4 wake-up configuration
00
NO wake-up capability
01
Wake-up on rising edge - or high level
10
Wake-up on falling edge - or low level
11
Wake-up on any edge
WU_IO4_1:0
Reset condition Power on reset
Table 25. INIT_WU1 description and configuration of the bits (default value in bold)...continued
13.3.3 INIT_WU2
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
0
0
0
0
1
1
P
WU_IO5_
1
WU_IO5_
0
CAN_
DIS_CFG
CAN_
WU_TO
0
LIN_
J2602_
DIS
LIN_SR_1 LIN_SR_0
 
MISO
SPI_G
WU_G
CAN_G
LIN_G
IO_G
VPRE
_G
VCORE
_G
VOTHERS_
G
WU_IO5_
1
WU_IO5_
0
CAN_
DIS_CFG
CAN_
WU_TO
RES
ERVED
LIN_
J2602_
DIS
LIN_SR_1 LIN_SR_0
Table 26. INIT_WU2 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
 
MISO
SPI_G
WU_G
CAN_G
LIN_G
IO_G
VPRE
_G
VCORE
_G
VOTHERS_
G
WU_IO5_
1
WU_IO5_
0
CAN_
DIS_CFG
CAN_
WU_TO
RES
ERVED
LIN_
J2602_
DIS
LIN_SR_1 LIN_SR_0
FS6500-FS4500-ASILD
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 8 — 5 August 2024
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