FS6500 datasheet(39/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

12.3 Deep fail-safe state

When the deep fail-safe function is enabled, the fail-safe state machine monitors and counts the number

of faults happening, in case of fault detection (see Section 12.5.3). As soon as either the fault error counter

reaches its final value or the RESET pin remains asserted low for more than 8.0 s, the device moves to deep

fail-safe state in the functional state diagram (Figure 16).

When the device is in deep fail-safe state, all the regulators are off (except VKAM if VKAM was on), RSTB,

FS0B, and FS1B are activated. To exit this state, a key off/key on action is needed. IO_0 is usually connected

to key signal. Key off (IO_0 low) moves the device to LPOFF-deep FS, and key on (IO_0 high) wakes up the

device.

During power up phase, the 8.0 s timer starts when the fail-safe state machine enters in the ’Wait_VPRE’ state

and stops when the RSTB pin is released. During ’INIT_FS’ state, the 8.0 s timer can be disabled in the register

INIT_FS_IMPACT. During ’normal WD’ state, the 8.0 s timer is activated at each RSTB pin assertion.

12.4 Functional state diagram

aaa-037745

- RSTB/FSxB asserted low

- RSTB asserted low

- RSTB released, FSxB asserted low

- Unlock SPI init registers

- 256 ms open window

- RSTB released, FSxB asserted low

- Start WD windowing

- RSTB delay running

- Unlock SPI init registers

- SPI init registers locked

- SPI config

- VCORE/VAUX/VCCA OFF

- VPRE/VCAN OFF

- Fail Safe OFF

- VKAM/LDT ON

- VPRE/VCAN/VCORE/VAUX/VCCA OFF

- VKAM/LDT ON

- OSC Main ON

- Fail Safe ON

- RSTB asserted low

- FSxB asserted low

- RSTB/FSxB asserted low

- 8 s timer starts

- RSTB/FSxB asserted low

- 8 s timer reset

- RSTB/FSxB asserted low

- 8 s timer running

- FSxb asserted low

LBIST

Power Down

From

Anywhere

ABIST1

Release

RTSB

Wait

VPRE

Wait

VREG

SELECT pin

configuration

ABIST2

(VAUX/FS1B)

Assert RSTB

INIT MAIN

Assert FSxB

INIT_FS

NORMAL_WD

FAIL SAFE STATE MACHINE

MAIN STATE MACHINE

LBIST Done

VPRE > VPRE_UV

VPRE < VPRE_UV

1 ms elapsed

VCORE > VCORE_UV

VCCA > VCCA_UV

ABIST1 Done

External

RST

No activate RSTB &

RSTB delay expired

Activate

RSTB

External

RST

Activate RST

or WD Not OK

External

RST

No external RST and

No activate RSTB

WD OK

PORB = 1 and

VPRE > VPRE_UV

PORB = 0

Power Down

From

Anywhere

Waits

Fail-

safe

VPRE

Deep

Fail-safe

SELECT pin

configuration

NORMAL

MODE

LPOFF-

SLEEP

Wake up

LPOFF-

Auto WU

LPOFF-

DEEP FS

VCORE/

VAUX/

VCCA ON

Buck or

Buck Boost

configuration

detection

PORB = 1 &

Fail-safe Reg. ON &

VSUP < VSUP_UV_5

VSUP < VSUP_UV_L

1.0 ms

SPI command

CAN, LIN

IOs or LDT

INIT INT

(reg. writing)

120 µs

VPRE > VPRE_UV

VSUP > VSUP_UV_5

SPI command

VSUP < VSUP_UV_5

VSUP <

VSUP_UV_5

1 ms

Rise IO_0

VPRE_UV_4P3

or SPI command

No DFS and

RST delay = 8 s

DFS &

(RST delay = 8 s or

FLT_err_count = 6)

VPRE_UV_4P3

IO_0 = 0

PORB = 1

Activate

RST

Activate

FSx

Figure 16. Simplified state diagram

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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