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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

12.5.2 Watchdog operation

A windowed watchdog is implemented in the FS6500/FS4500 and is based on the "question/answer" principle

(challenger). The watchdog must be continuously triggered by the MCU in the open watchdog window,

otherwise an error is generated. The error handling and watchdog operations are managed by the fail-safe state

machine. For debugging purpose, this functionality can be inhibited by setting the right voltage on the DEBUG

pin at start-up.

The watchdog window duration is selectable through the SPI during the INIT_FS phase or in normal mode. The

following values are available: 1.0 ms, 2.0 ms, 3.0 ms, 4.0 ms, 6.0 ms, 8.0 ms, 12 ms, 16.0 ms, 24 ms, 32 ms,

64 ms, 128 ms, 256 ms, 512 ms, and 1024 ms. The watchdog can also be inhibited through the SPI register in

INIT_FS phase to allow "reprogramming" (i.e. at vehicle level thru CAN).

An 8-bit pseudo-random word is generated by implementing a linear feedback shift register in the FS6500/

FS4500. The MCU can send the seed of the LFSR or use the LFSR generated by the FS6500/FS4500 during

the INIT phase and performs a pre-defined calculation. The result is sent through the SPI during the "open"

watchdog window and verified by the FS6500/FS4500. When the result is right, a new LFSR is generated and

the watchdog window is restarted. When the result is wrong, the WD error counter is incremented, the watchdog

window is restarted, an INTB is generated, and the LFSR value is not changed. Any access to the WD register

during the "closed" watchdog window is considered a wrong WD refresh.

12.5.2.1 Normal operation (first watchdog refresh)

At power up, when the RSTB is released as high (after around 16.5 ms), the INIT phase starts for a maximum

duration of 256 ms, and this is considered as a fully open watchdog window. During this initialization phase the

MCU sends the seed for the LFSR, or uses the default LFSR value generated by the FS6500/FS4500 (0xB2),

available in the WD_LFSR register (Table 90). Using this LFSR, the MCU performs a simple calculation based

on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D.

aaa-037747

LFSR_OUT[7:0]

WD_answer[7:0]

NOT

Figure 18. Watchdog answer calculation

The MCU sends the results in the WD_ANSWER register (Table 92). When the watchdog is properly refreshed

during the open window, the 256 ms open window is stopped and the initialization phase is finished. A new

LFSR is generated and available in the WD_LFSR register (Table 90). If the watchdog refresh is wrong or if

the watchdog is not refreshed during this 256 ms open window (INIT_FS phase), the device asserts the RSTB,

FS0B, and the fault error counter is incremented by '1'.

After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed

windows are defined either by the configuration made during initialization phase in the WD_WINDOW register

(Table 88), or by the default value already present in this register (3.0 ms).

12.5.2.2 Normal watchdog refresh

The watchdog must be refreshed during every open window of the window period configured in the register

WD_ANSWER. Any WD refresh restarts the window. This ensures the synchronization between MCU and

FS6500/FS4500.

The duration of the 'window' is selectable through the SPI with no access restriction, meaning the window

duration can be changed in the INIT phase or normal mode. Doing the change in normal operation allows the

system integrator to configure the watchdog window duration on the fly:

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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