SC28L202 datasheet(33/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

CRx – Command Register Extension, A and B

CR is used to write commands to the DUART.

Bit 7

Bit 6

Bit 5

Bit 4:0

Lock Tx and Rx Enables

Enable Tx

Enable Rx

Command Register codes.

0 = lock Rx & Tx state

1 = Change Rx & Tx state

0 = disable

1 = enable

0 = disable

1 = enable

(See Command Register Table)

CR[7] – Lock Tx and Rx enables.

If reset, the transmitter and receiver enable bits, CR[6:5] are not

significant. The enabled/disabled state of a receiver or transmitter

can be changed only if this bit is a “1” during the time of the write to

the command register.

WRITES TO THE LOWER 5 BITS OF THE CR WOULD USUALLY

HAVE CR[7]

AT “0” to maintain the condition of the receiver and transmitter. The

bit provides a mechanism for writing commands to a channel, via

CR[4:0], without the necessity of keeping track of or reading the

current enable status of the receiver and transmitter.

CR[6] – Enable Transmitter

A one written to this bit enables operation of the transmitter. The

TxRDY status bit will be asserted. When disabled by writing a zero

to this bit, the command terminates transmitter operation and resets

the TxRDY and Tx Idle status bits returning the transmitter to its idle

state . However, if a character is being transmitted or if characters

are loaded in the TxFIFO when the transmitter is disabled, the

transmission of the all character(s) is completed before assuming

the inactive state.

CR[5] – Enable Receiver

A one written to this bit enables operation of the receiver. The

receiver immediately begins the search for and the verification the

start bit. If a zero is written, this command terminates operation of

the receiver immediately – a character being received will be lost.

The command has no effect on the receiver status bits or any other

control registers. The data in the RxFIFO will be retained and may

be read. If the receiver is re–enabled subsequent data will be

appended to that already in the RxFIFO. If the special wake–up

mode is programmed, the receiver operates even if it is disabled

(see Wake–up Mode).

CR[4:0] – Miscellaneous Commands (See Table below)

The encoded value of this field can be used to specify a single

command as follows:

• 00000 No command.

• 00001 Reserved

• 00010 Reset receiver. Immediately resets the receiver as if

hardware reset had been applied. The receiver is reset and the

FIFO pointer is reset to the first location effectively discarding all

unread characters in the FIFO.

• 00011 Reset transmitter. Immediately resets the transmitter as if a

hardware reset had been applied. The transmitter is reset and the

FIFO pointer is reset to the first location effectively discarding all

untransmitted characters in the FIFO.

• 00100 Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]). It is used in either character or block mode. In block

mode it would normally be used after the block is read.

• 00101 Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be cleared to

zero.

• 00110 Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active and the

TxFIFO is empty then the break begins when transmission of the

current character is completed. If there are characters in the

TxFIFO, the start of break is delayed until all characters presently

in the TxFIFO and any subsequent characters loaded have been

transmitted. (Tx Idle must be true before break begins).

The transmitter must be enabled to start a break.

• 00111 Stop break. The TxD line will go high (marking) within two

bit times. TxD will remain high for one bit time before the next

character is transmitted.

• 01000 Assert RTSN. Causes the RTSN output to be asserted

(low).

• 01001 Negate RTSN. Causes the RTSN output to be negated

(high).

NOTE: The two commands above actually reset and set,

respectively, the I/O0 B (Channel A) or I/O1 B (Channel B)

pin associated with the OPR register. (See SOPR and

ROPR registers I/O pin control.

• 01010 Set C/T Receiver time out mode on

• 01011 Set MR Pointer to 0

• 01100 Set C/T Receiver time out mode off

• 01101 Block error status accumulation on FIFO entry. Allows the

“received break”, “framing error” and “parity error” bits to be set as

the received character is loaded to the RxFIFO. (normally these

bits are set on reading of the data from the RxFIFO) Setting this

mode can give information about error data up to 256 bytes earlier

than the normal mode. However it clouds the ability to know

precisely which byte(s) are in error.

• 01110 Power Down Mode On

• 01111 Disable Power Down Mode

• 10000 Transmit an Xon Character

• 10001 Transmit an Xoff Character

• 10010 C/T start sets the counter timer to the value of the

counter/timer preset register and starts the counter.

• 10011 C/T stop Effectively stops the counter/timer, captures the

last count value and resets the counter ready status bit in the ISR

• 10100 Reserved

• 10101 Reserved.

• 10110 Transmitter resume command (This command is not active

in “Auto–Transmit mode”). A command to cancel a previous Host

Xoff command. Upon receipt, the channel’s transmitter will

transfer a character, if any, from the TxFIFO and begin

transmission.

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