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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC28L202 датащи(PDF) 63 Page - NXP Semiconductors |
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SC28L202 датащи(HTML) 63 Page - NXP Semiconductors |
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63 / 77 page  Philips Semiconductors Objective specification SC28L202 Dual UART 2000 Feb 10 57 AC CHARACTERISTICS1,2,3 (NOMINAL 5 VOLTS) Vcc = 5v ± 10% Ta = – 40 to +85 _C unless otherwise specified LIMITS4 Symbol Parameter Min Typ Max UNIT Reset timing (See Figure 3) tRES Reset Pulse Width 100 18 ns Bus Timing5 (See Figure ___) t*AS A6–A0 setup time to RDN, WRN Low 10 6 ns t*AH A6–A0 hold time from RDN, WRN low 20 ns t*CS CEN setup time to RDN, WRN low 0 ns t*CH CEN Hold time from RDN. WRN Hi 0 ns t*RW WRN, RDN pulse width (Low time) 15 11 ns t*DD Data valid after RDN low (125 pf load) See loading table for smaller loads 15 40 ns t*DA RDN low to data bus active6 0 ns t*DF Data bus floating after RDN or CEN high 20 ns t*DI RDN or CEN high to data bus invalid7 0 ns t*DS Data bus setup time before WRN or CEN high (write cycle) 25 17 ns t*DH Data hold time after WRN high 0 –15 ns t*RWD High time between read and/or write cycles5,7 15 12 ns Port Timing5 (See Figure 7) t*PS Port in setup time before RDN low (Read IP ports cycle) 0 –20 ns t*PH Port in hold time after RDN high 0 –20 ns t*PD OP port valid after WRN or CEN high (OPR write cycle) 40 60 ns Interrupt Timing (See Figure 8) INTRN (or I/O(7:3)B when used as interrupts) negated from: Read RxFIFO (RxRDY/FFULL interrupt) 40 60 ns Write TxFIFO (TxRDY interrupt) 40 60 ns t*IR Reset Command (delta break change interrupt) 40 60 ns Stop C/T command (Counter/timer interrupt 40 60 ns Read IPCR (delta input port change interrupt) 40 60 ns Write IMR (Clear of change interrupt mask bit(s)) 40 60 ns Clock Timing (See Figure 9) t*CLK X1/CLK high or low time 30 20 ns f*CLK X1/CLK frequency (7.0 to 16.2 MHz with crystal) 1.0 14.7 50 MHz f*CTC C/T Clk (IP2) high or low time (C/T external clock input) 30 20 ns f*CTC C/T Clk (IP2) frequency8 0 MHz t*RX RxC high or low time (16X) 30 ns f*RX RxC Frequency (16X) 0 50 MHz RxC Frequency (1x)8,9 0 3 MHz t*TX TxC High or low time (16X) 30 ns f*TX TxC frequency (16X) 50 MHz TxC frequency (1X)8,9 0 3 MHz Transmitter Timing (See Figure 12) t*TXD TxD output delay from TxC low (TxC input pin) 40 60 ns t*TCS Output delay from TxC output pin low to TxD data output 6 30 ns Receiver Timing (See Figure 13) t*RXS RxD data setup time to RxC high 50 40 ns t*RXH RxD data hold time from RxC high 50 40 ns 68000 or Motorola bus timing (See Figure ___) tDCR DACKN Low (read cycle) from X1 High 15 20 ns TDCW DACKN Low (write cycle) from X1 High 15 20 ns TDAH DACKN High from CSN or IACKN high 8 10 ns tDAT DACKN High impedance from CSN or IACKN high 8 10 ns tCSC CSN or IACKN setup time to X1 high for minimum DACKN cycle 10 8 ns |
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