SC28L202 datasheet(44/77 Pages) PHILIPS

44 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

BCRx – Bidding Control Register – Xon/Xoff, A and B

Bits 7:0

MSBs of an Xon/Xoff interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for a Xon/Xoff interrupt.

BCRA – Bidding Control Register – Address, A and B

Bits 7:0

MSBs of an address recognition event interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for an address recognition event interrupt.

BCR C/T – Bidding Control Register –C/T, 0 and 1

Bits 7:0

MSBs of a counter/timer event interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for a counter/timer event interrupt.

BCRLBE – Bidding Control Register – Received Loop Back Error

Bits 7:0

MSBs of a received loop back error event interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for the received loop back error interrupt.

Registers of the I/O ports

IPCRL – Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B)

Bit 7

Bit 6

Bit 7

Bit 6

Bit 3

Bit 2

Bit 1

Bit 0

∆I/O3 n

change

∆I/O2 n

change

∆I/O1 n

change

∆I/O0 n

change

I/O3 n state

I/O2 n state

I/O1 n state

I/O0 n

state

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

Reads the actual logic level at the pin.

1 = high level; 0 = low level

This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each

pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.

IPCRU – Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B)

Bit 7

Bit 6

Bit 7

Bit 6

Bit 3

Bit 2

Bit 1

Bit 0

∆I/O7 n change

∆I/O6 n change

∆I/O5 n change

∆I/O4 n change

I/O7 n state

I/0n6 state

I/O5 n state

I/O4 n state

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

Reads the actual logic level at the pin.

1 = high level; 0 = low level

This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each

pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.

IPR – Input Port Register, A and B (n = A for A, n = B for B)

Bits 7:0

Logical levels of I/O(7:0)n

IPCE – Input Change Detect Enable, A and B (n = A for A, n = B for B)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

∆I/O7 n enable

∆I/O6 n enable

∆I/O5 n enable

∆I/O4 n enable

∆I/O3 n enable

∆I/O2 n enable

∆I/O1 n enable

∆I/O0 n enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

0 = disable

1 = enable

IPCE[7:0] bits activate the input change of state detectors. If a pin is configured as an output, the change of state detectors, if enabled, continue

to be active and will show a change of state as the I/P port changes.

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