SC28L202 datasheet(46/77 Pages) PHILIPS

46 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

ROPR A and ROPR B – Reset ROPR Output Port Bits (OPR A and OPR B)

ROPR [7:0] – Ones in the byte written to the ROPR will cause the

corresponding bit positions in the OPR to set to 0. Zeros have no

effect. This allows software to reset individual bits with our keeping a

copy of the OPR bit configuration. One register for each channel

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Reset OPR

Bits

OPR 7

OPR 6

OPR 5

OPR 4

OPR 3

OPR 2

OPR 1

OPR 0

1=reset bit

0=no change

1=reset bit

0=no

change

1=reset bit

0=no

change

1=reset bit

0=no

change

1=reset bit

0=no

change

1=reset bit

0=no

change

1=reset bit

0=no

change

1=reset bit

0=no change

OPR – Output Port Register, A and B (n = A for A, n = B for B)

The output pins (I/O pins) drive the data written to this register.

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OPR

I/O7 n

I/O6 n

I/O5 n

I/O4 n

I/O3 n

I/O2 n

I/O1 n

I/O0 n

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

0=Pin High

1=Pin Low

This register is set by the SOPR and ROPR above.

THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS

The purpose of including previous functionality is to allow users to

call communications code that may be used in former systems.

When the registers in this lower 16–position address space is used

it will revoke programming done in the upper address space where

the addresses are duplicated. If functions have been called from

upper address space that DO NOT exist in the lower address space

they will remain active. It is therefore recommended that the “Reset

to C92 “ command be issued before calling code written for older

devices. This is just recommended. If one wishes to enhance

previous code by using Xon/Xoff, for example, there is no restriction

against it. These registers provide the original functionality of

previous Philips DUARTs: SCN2681, SCN68681, SCC2691,

SCC68692, SC26C92 and SC28L92.

Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)

Address

READ (RDN = 0)

WRITE (WRN = 0)

Mode Register A (MR0 A, MR1 A, MR2 A)

Status Register A (SR A)

Clock Select Register A (CSR A )

Reserved

Command Register A (CR A)

Rx Holding Register A (RxFIFO A)

Tx Holding Register A (TxFIFO A)

Input Port Change Register (IPCR)

Aux. Control Register (ACR)

Interrupt Status Register (ISR)

Interrupt Mask Register (IMR)

Counter/Timer Upper (CTPU)

C/T Upper Preset Register (CTPU)

Counter/Timer Lower (CTPL)

C/T Lower Preset Register (CTPL)

Mode Register B (MR0 B, MR1 B, MR2 B)

Status Register B (SR B)

Clock Select Register B (CSR B )

Reserved

Command Register B (CR B)

Rx Holding Register B (RxFIFO B)

Tx Holding Register B (TxFIFO B)

IVR or general purpose register

Input Port (IPR) I/O(6:0) A

Output Port Confide. Register (OPCR) I/O(7:2) B

Start Counter Command (C/T 0)

Set Output Port Bits Command (SOPR) I/O(7:0) B

Stop Counter Command (C/T 0)

Reset output Port Bits Command (ROPR) I/O(7:0) B

NOTE: The three MR Registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and

transmitter enable bits)

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