SC28L202 datasheet(22/77 Pages) PHILIPS

22 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

Interrupt Arbitration and IRQN generation

Interrupt arbitration is the process used to determine that an

interrupt request should be presented to the host. The arbitration is

carried out between the ”Interrupt Threshold” and the ”sources”

whose interrupt bidding is enabled by the IMR. The interrupt

threshold is part of the ICR (Interrupt Control Register) and is a

value programmed by the user. The ”sources” present a value to the

interrupt arbiter. That value is derived from four fields: the channel

number, type of interrupts source, FIFO fill level, and a

programmable value. The interrupt request (IRQN) will be asserted

only when one or more of these values exceeds the threshold value

in the interrupt control register will.

Following assertion of the IRQN the host will either assert IACKN

(Interrupt Acknowledge) or will use the command to ”Update the

CIR”. At the time either action is taken the CIR will capture the value

of the source that is prevailing in the arbitration process. (Call this

value the winning bid).

The Sclk drives the arbitration process. It evaluates the 12 bits of

the arbitration bus at

½ the Sclk rate developing a value for the CIR

every two Sclk cycles. New arbitration values presented to the

arbitration block during an arbitration cycle will be evaluated in the

next arbitration cycle.

For sources other than receiver and transmitters the user may set

the high order bits of an interrupt source’s bid value, thus tailoring

the relative priority of the interrupt sources. The fill level of their

respective FIFOs controls the priority of the receivers and

transmitters. The more filled spaces in the RxFIFO the higher the bid

value; the more empty spaces in the TxFIFO the higher its priority.

Channels whose programmable high order bits are set will be given

interrupt priority higher than those with zeros in their high order bits,

thus allowing increased flexibility. The transmitter and receiver bid

values contain the character counts of the associated FIFOs as high

order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids

with a progressively higher priority for interrupt service. Similarly, as

empty space in a transmitter’s TxFIFO increases, its interrupt

arbitration priority increases.

The programmable fields allow the software to adjust the authority or

value of the bid for those devices not having a FIFO.

For example: The break condition is sometimes used to signal a

starting point in a continuous stream of data. A Continuous running

weather report or stock market “ticker–tape” report needs breaks in

the data so that a receiver knows where the data starts. Once start

of the break is detected it is important to reset the “change of break “

interrupt so that this bit can signal the condition of the break ending.

This is signaled by the ‘L202 the setting another change of break

event in the ISR. Since it is assumed the data will be starting very

soon after the end of break it is important to give the change of

break condition a high priority. This may be accomplished by setting

the arbitration value for the “change of break” to a high value. The

value in the “change of break programmable field” in Table 1 would

be 0x7F.

IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert

the IACKN signal low. This will cause the DUART to generate an

IACKN cycle in which the condition of the interrupting device is

determined. When IACKN asserts, the last valid interrupt number is

captured in the CIR. The value captured presents most of the

important details of the highest priority interrupt at the moment the

IACKN (or the ”Update CIR” command) was asserted.

The Dual UART will respond to the IACKN cycle with an interrupt

vector. The interrupt vector may be a fixed value, the content of the

Interrupt Vector Register, or when ”Interrupt Vector Modification” is

enabled via ICR, it may contain codes for the interrupt type and/or

interrupting channel. This allows the interrupt vector to steer the

interrupt service directly to the proper service routine. The interrupt

value captured in the CIR remains until another IACKN cycle occurs

or until an ”Update CIR” command is given to the DUART. The

interrupting channel and interrupt type fields of the CIR set the

current ”interrupt context” of the DUART. The channel component of

the interrupt context allows the use of Global Interrupt Information

registers that appear at fixed positions in the register address map.

For example, a read of the Global RxFIFO will read the channel B

RxFIFO if the CIR interrupt context is channel B receiver. At another

time read of the GRxFIFO may read the channel A RxFIFO (CIR

holds a channel A receiver interrupt) and so on. Global registers

exist to facilitate qualifying the interrupt parameters and for writing to

and reading from FIFOs without explicitly addressing them.

The CIR will load with x’00 if IACKN or Update CIR is asserted when

the arbitration circuit is NOT asserting an interrupt. In this condition

there is no arbitration value that exceeds the threshold value. When

Interrupt vector modification is active in this situation the interrupt

vector bits associated with the CIR will all be zero.

Global Registers

The ”Global Registers”, 10 in all, are driven by the interrupt system.

They are defined by the content of the CIR (Current Interrupt

are indirect registers pointed to by the content of the CIR. The list of

global register follows:

• GIBCR The byte count of the interrupting FIFO

• GICR

Channel number of the interrupting channel

• GITR

Type identification of interrupting channel

• GRxFIFO Pointer to the interrupting receiver FIFO

• GTxFIFO Pointer to the interrupting transmitter FIFO

A read of the GRxFIFO will give the content of the RxFIFO that

presently has the highest bid value. The purpose of this system is to

enhance the efficiency of the interrupt system. The global registers

and the CIR update procedure are further described in the Interrupt

Arbitration system

Polling, (Normal and using the CIR)

Many users prefer polled to interrupt driven service where there are

not a large number of fast data channels and/or the host CPU’s

other interrupt overhead is low. The Dual UART is functional in this

environment.

The most efficient method of polling is the use of the ”update CIR”

command (with the interrupt threshold set to zero) followed by a

read of the CIR. This dummy write cycle will perform the same CIR

capture function that an IACKN falling edge would accomplish in an

interrupt driven system. A subsequent read of the CIR, at the same

address, will give information about an interrupt, if any. If the CIR

type field contains 0s, no interrupt is awaiting service. If the value is

non–zero, the fields of the CIR may be decoded for type; channel

and character count information. Optionally, the global interrupt

registers may be read for particular information about the interrupt

status or use of the global RxD and TxD registers for data transfer

as appropriate. The interrupt context will remain in the CIR until

another update CIR command or an IACKN cycle is initiated by the

host CPU occurs. The CIR loads with x’00 if Update CIR is asserted

when the arbitration circuit has NOT detected an arbitration value

that exceeds the threshold value of the ICR. The global registers

and CIR may be used as “vectors” to the service type required.

SC28L202 датащи(PDF) 22 Page - NXP Semiconductors

SC28L202 датащи(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL