SC28L202 datasheet(49/77 Pages) PHILIPS

49 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

MR1 Mode Register 1

Bit 7

BIT 6

BIT 5

Bit (4:3)

BIT 2

Bits (1:0)

MR1 A

MR1 B

CONTROLS

RTS

RxINT

BIT 1

ERROR

MODE

PARITY MODE

PARITY

TYPE

BITS PER

CHARACTER

0 = No

1 = Yes

0 = RxRDY

1 = FFULL

0 = Char

1 = Block

00 = With Parity

01 = Force Parity

10 = No Parity

11 = Multi–drop Mode

0 = Even

1 = Odd

00 = 5

01 = 6

10 = 7

11 = 8

NOTE: * In block error mode the block error conditions must be cleared by using the error reset command (command 0x40) or a receiver reset.

MR1 A is accessed when the Channel A MR pointer points to MR1.

The pointer is set to MR1 by RESET or by a ‘set pointer’ command

applied via CR command 1. After reading or writing MR1 A, the

pointer will point to MR2 A.

MR1 A[7] – Channel A Receiver Request–to–Send Control (Flow

Control)

This bit controls the deactivation of the RTSN A output (I/O0 B) by

the receiver. This output is normally asserted by setting OPR[0]B

and negated by resetting OPR[0]B.

MR1 A[7] = 1 causes RTSN A to be negated (I/O0 B is driven to a ‘1’

[VCC]) upon receipt of a valid start bit if the Channel A FIFO is full.

This is the beginning of the reception of the ninth byte. If the FIFO is

not read before the start of the tenth byte, an overrun condition will

occur and the tenth byte will be lost. However, the bit in OPR[0] is

not reset and RTSN A will be asserted again when an empty FIFO

position is available. This feature can be used for flow control to

prevent overrun in the receiver by using the RTSN A output signal to

control the CTSN input of the transmitting device.

MR1[6] – Receiver interrupt control bit 1. See description under

MR0[6].

MR1 A[5] – Channel A Error Mode Select

This bit select the operating mode of the three FIFOed status bits

(FE, PE, received break) for Channel A. In the ‘character’ mode,

status is provided on a character–by–character basis; the status

applies only to the character at the top of the FIFO. In the ‘block’

mode, the status provided in the SR for these bits is the

accumulation (logical–OR) of the status for all characters coming to

the top of the FIFO since the last ‘reset error’ command for Channel

A was issued.

MR1 A[4:3| – Channel A Parity Mode Select

If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data

MR1 A[4:3] = 11 selects Channel A to operate in the special

multi–drop mode described in the Operation section.

MR1 A[2] – Channel A Parity Type Select

Selects the parity type (odd or even) if the “‘with parity” mode is

programmed by MR1 A[4:3], and the polarity of the forced parity bit if

the ‘force parity’ mode is programmed; no effect if ‘no parity’ is

programmed. In the special multi–drop mode it selects the polarity of

the A/D bit.

MR1 A[1:0] – Channel A Bits Per Character Select

This field selects the number of data bits per character to be

transmitted and received. The character length does not include the

start, parity, and stop bits.

MR2 A is accessed when the Channel A MR pointer points to MR2,

which occurs after any access to MR1 A. Accesses to MR2 A do not

change the pointer.

MR2 Mode Register 2

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR2 A

MR2 B

CHANNEL MODE

Tx CONTROLS RTS

CTS

ENABLE Tx

STOP BIT LENGTH

NOTE: Add 0.5 to binary codes 0 – 7 for 5 bit character lengths.

00 = Normal

01 = Auto–Echo

10 = Local loop

11 = Remote loop

0 = No

1 = Yes

0 = No

1 = Yes

0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813

1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875

2 = 0.688 6 = 0.938 A = 1.688 E = 1.938

3 = 0.750 7 = 1.000 B = 1.750 F = 2.000

NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed

for 5 bits/char.

See description in the previous MR2 description

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