ADIS16501SLASHPCBZ datasheet(19/45 Pages) AD

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Data Sheet

ADIS16501

THEORY OF OPERATION

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Rev. B | 19 of 45

CLOCK CONTROL

The ADIS16501 provides four modes of operation with respect to

the source of the sampling and processing clock (see the frequency

sampling clock (fSM) in Figure 29): internal, direct input sync, scaled

sync, and output sync. The MSC_CTRL register, Bits[3:2] (see

Table 106 and Table 107) provide user selection of these modes.

Internal Clock Mode

Setting Register MSC_CTRL, Bits[3:2] = 00 selects the internal

clock mode and is the default. In this mode, the ADIS16501 uses

an internally generated clock that has a nominal frequency of 2000

Hz to drive sampling and data processing for each sensor and

associated signal chain.

Direct Input Sync Mode

Setting Register MSC_CTRL, Bits[3:2] = 01 selects direct input

sync mode and allows fSM to come directly from an external clock to

control the sensor sampling using the SYNC pin as an input. When

operating in input sync mode, the ADIS16501 performs best when

the external clock frequency (fSYNC) is between 1900 Hz and 2100

Hz.

Scaled Sync Mode

Setting Register MSC_CTRL, Bits[3:2] = 10 selects scaled sync

mode, which supports use of an external sync clock between

1 Hz and 128 Hz that can come from video systems or global

positioning systems (GPSs). When operating in scaled sync mode,

the frequency of the sample clock is equal to the product of the

external clock scale factor, KECSF (from the UP_SCALE register,

see Table 108 and Table 109), and the frequency of the clock signal

on the SYNC pin. As in input sync mode, the ADIS16501 performs

best when fSM is between 1900 Hz and 2100 Hz.

Changes to the UP_SCALE register value reset the clock multipli-

cation phase-locked loop (PLL) and restart the locking process.

The locking process starts with an input reference clock edge

resetting the feedback clock edge, and lock is declared when time

differences between these two edges are ≤100 µs.

For example, when using a 1 Hz input signal, set UP_SCALE =

0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of

2000 SPS for the inertial sensors and their signal processing. Use

the following sequence on the DIN pin to configure UP_SCALE for

this scenario: 0xE2D0, then 0xE307.

Output Sync Mode

When Register MSC_CTRL, Bits[3:2] = 11, the ADIS16501 oper-

ates in output sync mode, which is the same as internal clock mode

except that the SYNC pin pulses when the internal processor col-

lects data from the inertial sensors. Figure 30 provides an example

of this signal.

Figure 30. Sync Output Signal, Register MSC_CTRL, Bits[3:2] = 11

BARTLETT WINDOW FILTER

The Bartlett window filter is a finite impulse response (FIR) filter

(see Figure 31) that contains two averaging filter stages in a

cascade configuration. The FILT_CTRL register (see Table 103)

provides the configuration controls for this filter.

Figure 31. Bartlett Window FIR Filter Signal Path

CALIBRATION

The inertial sensor calibration function for the gyroscopes and the

accelerometers has two components: factory calibration and user

calibration (see Figure 32).

Figure 32. Inertial Sensor Calibration Processing

The factory calibration of the gyroscope applies the following cor-

rection formulas to the data of each gyroscope:

ωXCωYCωZC =m11m12m13

m21m22m23

m31m32m33 ×

ωXωYωZ+bXbYbZ +

l11l12l13

l21l22l23

l31l32l33 +

aXCaYCaZC

where:

ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).

m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and

alignment correction.

ωX, ωY, and ωZ are the gyroscope outputs (precalibration).

bX, bY, and bZ provide bias correction.

l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear acceleration

correction.

aXC, aYC, and aZC are the accelerometer outputs (post calibration).

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