Data Sheet

ADIS16501

SPECIFICATIONS

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Rev. B | 5 of 45

1 This measurement is based on the deviation from a best fit linear model.

2 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at 105°C.

3 All specifications associated with the accelerometers relate to the full-scale range of ±14 g, unless otherwise noted.

4 The digital input/output signals use a 3.3 V system.

5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.

6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.

7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.

8 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.

9 Power supply current transients can reach 100 mA during initial startup or reset recovery.

TIMING SPECIFICATIONS

TA = 25°C and VDD = 3.3 V, unless otherwise noted.

Table 2.

Parameter

Description

Normal Mode

Burst Read Mode

Unit

Min

Typ

Max

Min

Typ

Max

fSCLK

Serial clock

0.1

10

0.1

1.1

MHz

tSTALL

Stall period between data

16

N/A1

µs

tREADRATE

Read rate

24

µs

tCS

Chip select to SCLK edge

200

200

ns

tDAV

DOUT valid after SCLK edge

25

25

ns

tDSU

DIN setup time before SCLK rising edge

25

25

ns

tDHD

DIN hold time after SCLK rising edge

50

50

ns

tSCLKR, tSCLKF

SCLK rise/fall times

5

12.5

5

12.5

ns

tDR, tDF

DOUT rise/fall times

5

12.5

5

12.5

ns

tSFS

CS high after SCLK edge

0

0

ns

t1

Input sync positive pulse width, direct sync mode, MSC_CTRL, Bits[3:2] =

01 (binary, see Table 107)

5

5

µs

tSTDR

Input sync to data ready valid transition, no SPI traffic, direct sync mode,

MSC_CTRL, Bits[3:2] = 01 (binary, see Table 107)

305

305

µs

Input sync to data ready valid transition, full SPI traffic2, direct sync mode,

MSC_CTRL, Bits[3:2] = 01 (binary, see Table 107)

405

405

µs

tNV

Data invalid time

23

23

µs

t2

Input sync period

500

500

µs

1 N/A means not applicable.

2 Full SPI traffic is defined as a transfer of 64 16-bit registers using an SCLK frequency of 2 MHz. Reading the sensor values from the previous data sample proportionally

increases the tSTDR on the current cycle.