ADIS16501SLASHPCBZ datasheet(25/45 Pages) AD

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Data Sheet

ADIS16501

THEORY OF OPERATION

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Rev. B | 25 of 45

Table 9. Group Delay with No Filtering, 370 Hz Bandwidth, MSC_CTRL, Bit 4 =

1 (Continued)

Inertial Sensor

Group Delay (ms)1

Gyroscope (Z-Axis)

1.54

1 In this context, latency represents the time between the motion (linear acceler-

ation and/or angular rate of rotation) and the time that the representative data

is available in the output data register.

When the FILT_CTRL register is not equal to 0, the group delay

contribution of the Bartlett window filter (in terms of sample cycles)

is equal to N (see Table 103). When the DEC_RATE register is not

equal to 0, the group delay contribution of the decimation filter (in

terms of sample cycles) is equal D + 1, divided by 2 (see Table

111).

Data Acquisition

The total latency is equal to the sum of the group delay and

the data acquisition time, which represents the time it takes the

system processor to read the data from the output data registers of

the ADIS16501. For example, when using the burst read function,

with an SCLK rate of 1 MHz, the data acquisition time is equal to

176 µs (11 segments × 16 SCLKs/segment × 1 µs/SCLK).

DEVICE CONFIGURATION

Each configuration register contains 16 bits (two bytes). Bits[7:0]

contain the low byte, and Bits[15:8] contain the high byte. Each byte

has its own unique address in the user register map (see Table 10).

Updating the contents of a register requires writing to both of its

bytes in the following sequence: low byte first, high byte second.

There are three parts to coding an SPI command (see Figure 40)

that write a new byte of data to a register: the write bit (R/W =

1), the address of the byte, [A6:A0], and the new data for that

location, [DC7:DC0]. Figure 46 shows a coding example for writing

0x0004 to the FILT_CTRL register (see Table 103). In Figure 46,

the 0xDC04 command writes 0x04 to Address 0x5C (lower byte),

and the 0xDD00 command writes 0x00 to Address 0x5D (upper

byte).

Figure 46. SPI Sequence for Writing 0x0004 to FILT_CTRL

MEMORY STRUCTURE

Figure 47 provides a functional diagram for the memory structure

of the ADIS16501. The flash memory bank contains the operational

code, unit specific calibration coefficients, and user configuration

settings. During initialization (power application or reset recover),

this information loads from the flash memory into the static ran-

dom access memory (SRAM), which supports all normal operation

including register access through the SPI port. Writing to a con-

figuration register using the SPI updates the SRAM location of

the register but does not automatically update its settings in the

flash memory bank. The manual flash memory update command

(Register GLOB_CMD, Bit 3, see Table 113) provides a convenient

method for saving all of these settings to the flash memory bank at

one time. A yes in the flash backup column of Table 10 identifies

the registers that have storage support in the flash memory bank.

Figure 47. SRAM and Flash Memory Diagram

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