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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9957/PCBZ датащи(PDF) 54 Page - Analog Devices |
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AD9957/PCBZ датащи(HTML) 54 Page - Analog Devices |
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54 / 60 page  AD9957 Rev. 0 | Page 54 of 60 Multichip Sync Register Address 0x0A, four bytes are assigned to this register. Table 26. Bit Descriptions for the Multichip Sync Register Bit(s) Mnemonic Description 31:28 Sync Validation Delay Default is 0000b. This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the delayed sync-in signal for the synchronization validation block in the synchronization receiver. 0: synchronization clock receiver disabled (default). 27 Sync Receiver Enable 1: synchronization clock receiver enabled. 0: synchronization clock generator disabled (default). 26 Sync Generator Enable 1: synchronization clock generator enabled. 0: synchronization clock generator coincident with the rising edge of the system clock (default). 25 Sync Generator Polarity 1: synchronization clock generator coincident with the falling edge of the system clock. 24 Not Available 23:18 Sync State Preset Value Default is 000000b. This 6-bit number is the state that the internal clock generator assumes when it receives a sync pulse. 17:16 Not Available 15:11 Sync Generator Delay Default is 00000b. This 5-bit number sets the output delay (in ~150 ps increments) of the synchronization generator. 10:8 Not Available 7:3 Sync Receiver Delay Default is 00000b. This 5-bit number sets the delay input delay (in ~150 ps increments) of the synchronization receiver. 2:0 Not Available |
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