AD9957SLASHPCBZ datasheet(52/60 Pages) AD

52 / 60 page

AD9957

Rev. 0 | Page 52 of 60

Bit

No.

Mnemonic

Description

0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate

and provide timing to the data assembler.

PDCLK Enable

1: the internal PDCLK signal appears at the PDCLK pin (default).

0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).

PDCLK Invert

1: inverted PDCLK polarity.

0: normal TxEnable polarity; Logic 0 is standby, Logic 1 is transmit (default).

TxEnable Invert

1: inverted TxEnable polarity; Logic 0 is transmit, Logic 1 is standby.

0: an I/Q data pair is delivered as I-data first followed by Q-data (default).

Q First Data

Pairing

1: an I/Q data pair is delivered as Q-data first followed by I-data.

0: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output in

the order listed (default).

Matched Latency

Enable

1: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output

simultaneously.

Ineffective when CFR1 Bits<25:24> = 01b.

0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on

the baseband signal path (default).

Data Assembler

Hold Last Value

1: when the TXENABLE pin is false, the data assembler ignores the input data and internally forces the last

value received on the baseband signal path.

0: enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization pulse

sampling error.

Sync Timing

Validation Disable

1: the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).

4:0

Not Available

Control Function Register 3 (CFR3)

Address 0x02, four bytes are assigned to this register.

Table 20. Bit Descriptions for CFR3 Register

Bit

No.

Mnemonic

Description