AD9957SLASHPCBZ datasheet(51/60 Pages) AD

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AD9957

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Bit

No.

Mnemonic

Description

0: assertion of the EXT_PWR_DWN pin affects full power-down (default).

External Power-

Down Control

1: assertion of the EXT_PWR_DWN pin affects fast recovery power-down.

Ineffective when Bits<25:24> = 01b.

0: disable power-down (default).

Auto Power-Down

Enable

1: when the TxEnable pin is Logic 0, the baseband signal processing chain is flushed of residual data and the

clocks are automatically stopped. Clocks restart when the TxEnable pin is a Logic 1.

0: configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default).

SDIO Input Only

1: configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode.

0: configures the serial I/O port for MSB first format (default).

LSB First

1: configures the serial I/O port for LSB first format.

Control Function Register 2 (CFR2)

Address 0x01, four bytes are assigned to this register.

Table 19. Bit Descriptions for CFR2 Register

Bit

No.

Mnemonic

Description

Valid only when CRF1<25:24> = 00b.

0: Pin D<17:0> configured as an 18-bit parallel port (default).

Blackfin Interface

(BFI) Mode

1: Pin D<5:4> configured as a dual serial port compatible with the Blackfin serial interface. Pin D<17:6>

and Pin D<3:0> become available as a 16-bit GPIO port.

Valid only when Bit 31 = 1.

0: the dual serial port (BFI) configured for MSB first operation (default).

Blackfin Bit Order

1: the dual serial port (BFI) configured for LSB first operation.

Valid only when Bit 31 = 1.

0: The dual serial port (BFI) configured to be compatible with Blackfin late frame sync operation (default).

Blackfin Early

Frame Sync Enable

1: the dual serial port (BFI) configured to be compatible with Blackfin early frame sync operation.

28:24

Not Available

This bit is effective without the need for an I/O update.

0: serial I/O programming is synchronized with external assertion of the I/O_UPDATE pin, which is

configured as in input pin (default).

Internal IO Update

Active

1: serial I/O programming is synchronized with an internally generated I/O update signal (the internally

generated signal appears at the I/O_UPDATE pin, which is configured as an output pin).

0: the SYNC_CLK pin is disabled; static Logic 0 output.

SYNC_CLK Enable

1: the SYNC_CLK pin generates a clock signal at ¼ fSYSCLK; used of synchronization of the serial I/O port

(default).

21:17

Not Available

0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default).

Read Effective

FTW

1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to

the DDS phase accumulator.

Ineffective unless Bit 23 = 1. Sets the prescale ratio of the divider that clocks the Auto I/O Update timer as

follows:

00: divide-by-1 (default).

01: divide-by-2.

10: divide-by-4.

15:14

IO Update Rate

Control

11: divide-by-8.

Ineffective unless Bit 31 = 0 and CFR1 Bits<25:24> = 00b.

0: PDCLK operates at the input data rate (default).

PDCLK Rate

Control

1: PDCLK operates at ½ the input data rate; useful for maintaining a consistent relationship between I/Q

words at the parallel data port and the internal clocks of the baseband signal processing chain.

0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default).

Data Format

1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary.

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