AD9957SLASHPCBZ datasheet(43/60 Pages) AD

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AD9957

Rev. 0 | Page 43 of 60

I/O_UPDATE—Input/Output Update

The I/O_UPDATE initiates the transfer of written data from

the I/O port buffer to active registers. I/O_UPDATE is active

on the rising edge and its pulse width must be greater than one

SYNC_CLK period. It is either an input or output pin depending

on the programming of the internal I/O update active bit.

SERIAL I/O TIMING DIAGRAMS

The diagrams below provide basic examples of the timing

relationships between the various control signals of the serial

I/O port. Most of the bits in the register map are not transferred

to their internal destinations until assertion of an I/O update,

which is not included in the timing diagrams that follow.

MSB/LSB TRANSFERS

The AD9957 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by Bit 0 in Control Function

high, the serial port is configured for LSB-first format. If LSB

first is active, all data, including the instruction byte, must

follow LSB-first convention. Note that the highest number

found in the bit range column for each register (see the Register

Map and Bit Descriptions section and Table 13) is the MSB and

the lowest number is the LSB for that register.

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 59. Serial Port Write Timing—Clock Stall Low

DO7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

DO6 DO5 DO4 DO3 DO2 DO1

DO0

Figure 60. 3-Wire Serial Port Read Timing—Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 61. Serial Port Write Timing—Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 62. 2-Wire Serial Port Read Timing—Clock Stall High

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